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src/cmd/asm/internal/arch/riscv64.go
// CSR symbolic names and whether that instruction expects a register // or an immediate source operand. func IsRISCV64CSRO(op obj.As) (imm bool, ok bool) { switch op { case riscv.ACSRRCI, riscv.ACSRRSI, riscv.ACSRRWI: imm = true fallthrough case riscv.ACSRRC, riscv.ACSRRS, riscv.ACSRRW: ok = true } return } var riscv64SpecialOperand map[string]riscv.SpecialOperand
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Wed Apr 01 04:17:57 GMT 2026 - 3K bytes - Click Count (0) -
doc/asm.html
</li> <li> <code>R0.UXTB</code> <br> <code>R0.UXTB<<imm</code>: <code>UXTB</code>: extract an 8-bit value from the low-order bits of <code>R0</code> and zero-extend it to the size of <code>R0</code>. <code>R0.UXTB<<imm</code>: left shift the result of <code>R0.UXTB</code> by <code>imm</code> bits. The <code>imm</code> value can be 0, 1, 2, 3, or 4.
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Fri Nov 14 19:09:46 GMT 2025 - 36.5K bytes - Click Count (0) -
docs/de/docs/features.md
Created: Sun Apr 05 07:19:11 GMT 2026 - Last Modified: Thu Mar 19 17:58:09 GMT 2026 - 10.3K bytes - Click Count (0)