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Results 1 - 5 of 5 for x12 (0.06 seconds)
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lib/fips140/v1.26.0.zip
MOVOU 80(DI), X12 PCLMULQDQ $0x00, X2, X12 PXOR X12, X10 MOVOU 96(DI), X12 MOVOU X12, X13 PCLMULQDQ $0x00, X3, X12 PXOR X12, X8 PCLMULQDQ $0x11, X3, X13 PXOR X13, X9 PSHUFD $0x4e, X3, X12 PXOR X12, X3 MOVOU 112(DI), X12 PCLMULQDQ $0x00, X3, X12 PXOR X12, X10 MOVOU 128(DI), X12 MOVOU X12, X13 PCLMULQDQ $0x00, X4, X12 PXOR X12, X8 PCLMULQDQ $0x11, X4, X13 PXOR X13, X9 PSHUFD $0x4e, X4, X12 PXOR X12, X4 MOVOU 144(DI), X12 PCLMULQDQ $0x00, X4, X12 PXOR X12, X10 MOVOU 160(DI), X12 MOVOU X12, X13 PCLMULQDQ...
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Jan 08 17:58:32 GMT 2026 - 660.3K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/riscv64validation.s
CXOR X10, X11, X12 // ERROR "rd must be the same as rs1" CXOR X5, X11 // ERROR "expected integer prime register in rs2" CXOR X10, X5 // ERROR "expected integer prime register in rd" CSUB X10, X11, X12 // ERROR "rd must be the same as rs1" CSUB X5, X11 // ERROR "expected integer prime register in rs2" CSUB X10, X5 // ERROR "expected integer prime register in rd"
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Nov 13 12:17:37 GMT 2025 - 42.1K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
VSETVLI X10, E32, MF8, TA, MA, X12 // 5776550d VSETVLI X10, E32, MF4, TA, MA, X12 // 5776650d VSETVLI X10, E32, MF2, TA, MA, X12 // 5776750d VSETVLI X10, E32, M1, TA, MA, X12 // 5776050d VSETVLI $15, E32, M1, TA, MA, X12 // 57f607cd VSETIVLI $0, E32, M1, TA, MA, X12 // 577600cd VSETIVLI $15, E32, M1, TA, MA, X12 // 57f607cd VSETIVLI $31, E32, M1, TA, MA, X12 // 57f60fcd VSETVL X10, X11, X12 // 57f6a580
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Sat Apr 04 05:25:40 GMT 2026 - 74.2K bytes - Click Count (0) -
lib/fips140/v1.0.0-c2097c7c.zip
MOVOU 80(DI), X12 PCLMULQDQ $0x00, X2, X12 PXOR X12, X10 MOVOU 96(DI), X12 MOVOU X12, X13 PCLMULQDQ $0x00, X3, X12 PXOR X12, X8 PCLMULQDQ $0x11, X3, X13 PXOR X13, X9 PSHUFD $0x4e, X3, X12 PXOR X12, X3 MOVOU 112(DI), X12 PCLMULQDQ $0x00, X3, X12 PXOR X12, X10 MOVOU 128(DI), X12 MOVOU X12, X13 PCLMULQDQ $0x00, X4, X12 PXOR X12, X8 PCLMULQDQ $0x11, X4, X13 PXOR X13, X9 PSHUFD $0x4e, X4, X12 PXOR X12, X4 MOVOU 144(DI), X12 PCLMULQDQ $0x00, X4, X12 PXOR X12, X10 MOVOU 160(DI), X12 MOVOU X12, X13 PCLMULQDQ...
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Sep 25 19:53:19 GMT 2025 - 642.7K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/riscv64error.s
MOVWU X5, (X6) // ERROR "unsupported unsigned store" MOVF F0, F1, F2 // ERROR "illegal MOV instruction" MOVD F0, F1, F2 // ERROR "illegal MOV instruction" MOV X10, X11, X12 // ERROR "illegal MOV instruction" MOVW X10, X11, X12 // ERROR "illegal MOV instruction" RORI $64, X5, X6 // ERROR "immediate out of range 0 to 63" SLLI $64, X5, X6 // ERROR "immediate out of range 0 to 63"
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Wed Apr 01 04:17:57 GMT 2026 - 27.2K bytes - Click Count (0)