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Results 1 - 10 of 40 for paddi (0.04 sec)

  1. src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules

    (AND <t> x:(MOVDconst [m]) n) && t.Size() == 4 && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(0,m,32)] n)
    
    // When PCRel is supported, paddi can add a 34b signed constant in one instruction.
    (ADD (MOVDconst [m]) x) && supportsPPC64PCRel() && (m<<30)>>30 == m => (ADDconst [m] x)
    
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 3.8K bytes
    - Viewed (0)
  2. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go

    		// If EH == 0, omit printing EH.
    		eh := inst.Args[3].(Imm)
    		if eh == 0 {
    			argList = inst.Args[:3]
    		}
    		buf.WriteString(inst.Op.String())
    
    	case "paddi":
    		// There are several extended mnemonics.  Notably, "pla" is
    		// the only valid mnemonic for paddi (R=1), In this case, RA must
    		// always be 0.  Otherwise it is invalid.
    		r := inst.Args[3].(Imm)
    		ra := inst.Args[1].(Reg)
    		str := opName
    		if ra == R0 {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:33 UTC 2023
    - 12.2K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/ppc64/obj9.go

    			break
    		}
    		if p.From.Offset&0xFFFF == 0 {
    			// The constant can be added using ADDIS
    			p.As = AADDIS
    			p.From.Offset >>= 16
    		} else if buildcfg.GOPPC64 >= 10 {
    			// Let the assembler generate paddi for large constants.
    			break
    		} else if (p.From.Offset < -0x8000 && int64(int32(p.From.Offset)) == p.From.Offset) || (p.From.Offset > 0xFFFF && p.From.Offset < 0x7FFF8000) {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 18:17:17 UTC 2024
    - 40.8K bytes
    - Viewed (0)
  4. src/vendor/golang.org/x/crypto/chacha20poly1305/chacha20poly1305_amd64.s

    	// Add in the state
    	PADDD ·chacha20Constants<>(SB), A0; PADDD ·chacha20Constants<>(SB), A1; PADDD ·chacha20Constants<>(SB), A2; PADDD ·chacha20Constants<>(SB), A3
    	PADDD state1Store, B0; PADDD state1Store, B1; PADDD state1Store, B2; PADDD state1Store, B3
    	PADDD state2Store, C0; PADDD state2Store, C1; PADDD state2Store, C2; PADDD state2Store, C3
    	PADDD ctr0Store, D0; PADDD ctr1Store, D1; PADDD ctr2Store, D2; PADDD ctr3Store, D3
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Nov 29 21:28:33 UTC 2023
    - 105.6K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/riscv/obj.go

    	if p.Spadj == 0 && ins.as == AADDI && ins.imm >= -(1<<12) && ins.imm < 1<<12-1 {
    		imm0 := ins.imm / 2
    		imm1 := ins.imm - imm0
    
    		// ADDI $(imm/2), REG, TO
    		// ADDI $(imm-imm/2), TO, TO
    		ins.imm = imm0
    		insADDI := &instruction{as: AADDI, rd: ins.rd, rs1: ins.rd, imm: imm1}
    		return []*instruction{ins, insADDI}
    	}
    
    	// LUI $high, TMP
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 77K bytes
    - Viewed (0)
  6. src/cmd/asm/internal/asm/testdata/riscv64.s

    	// 2.4: Integer Computational Instructions
    
    	ADDI	$2047, X5				// 9382f27f
    	ADDI	$-2048, X5				// 93820280
    	ADDI	$2048, X5				// 9382024093820240
    	ADDI	$-2049, X5				// 938202c09382f2bf
    	ADDI	$4094, X5				// 9382f27f9382f27f
    	ADDI	$-4096, X5				// 9382028093820280
    	ADDI	$4095, X5				// b71f00009b8fffffb382f201
    	ADDI	$-4097, X5				// b7ffffff9b8fffffb382f201
    	ADDI	$2047, X5, X6				// 1383f27f
    	ADDI	$-2048, X5, X6				// 13830280
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 22 04:42:21 UTC 2024
    - 16.7K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (Rsh16x64 <t> x y) && !shiftIsBounded(v) => (SRA  <t> (SignExt16to64 x) (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [64] y))))
    (Rsh32x8  <t> x y) && !shiftIsBounded(v) => (SRAW <t> x                 (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [32] (ZeroExt8to64  y)))))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  8. src/internal/chacha8rand/chacha8_amd64.s

    	REPLREG(SI, X1)
    	REPLREG(R8, X2)
    	REPLREG(R9, X3)
    	REPLREG(R10, X12)
    	REPLREG(R11, X13)
    	REPLREG(R12, X14)
    	REPLREG(R13, X15)
    	PADDD X0, X4
    	PADDD X1, X5
    	PADDD X2, X6
    	PADDD X3, X7
    	PADDD X12, X8
    	PADDD X13, X9
    	PADDD X14, X10
    	PADDD X15, X11
    	MOVOU X4, (4*16)(BX)
    	MOVOU X5, (5*16)(BX)
    	MOVOU X6, (6*16)(BX)
    	MOVOU X7, (7*16)(BX)
    	MOVOU X8, (8*16)(BX)
    	MOVOU X9, (9*16)(BX)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Dec 05 20:34:30 UTC 2023
    - 4.6K bytes
    - Viewed (0)
  9. src/sync/atomic/atomic_test.go

    func hammerStoreLoadInt64Method(t *testing.T, paddr unsafe.Pointer) {
    	addr := (*Int64)(paddr)
    	v := addr.Load()
    	vlo := v & ((1 << 32) - 1)
    	vhi := v >> 32
    	if vlo != vhi {
    		t.Fatalf("Int64: %#x != %#x", vlo, vhi)
    	}
    	new := v + 1 + 1<<32
    	addr.Store(new)
    }
    
    func hammerStoreLoadUint64(t *testing.T, paddr unsafe.Pointer) {
    	addr := (*uint64)(paddr)
    	v := LoadUint64(addr)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 18:37:29 UTC 2024
    - 71.4K bytes
    - Viewed (0)
  10. src/cmd/internal/obj/ppc64/asm9.go

    		}
    
    	case 23: /* and $lcon/$addcon,r1,r2 ==> oris+ori+and/addi+and */
    		if p.To.Reg == REGTMP || p.Reg == REGTMP {
    			c.ctxt.Diag("can't synthesize large constant\n%v", p)
    		}
    		d := c.vregoff(&p.From)
    		r := int(p.Reg)
    		if r == 0 {
    			r = int(p.To.Reg)
    		}
    
    		// With S16CON operand, generate 2 instructions using ADDI for signed value,
    		// with 32CON operand generate 3 instructions.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 13:55:28 UTC 2024
    - 156.1K bytes
    - Viewed (0)
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