register["FS7"] = riscv.REG_FS7
	register["FS8"] = riscv.REG_FS8
	register["FS9"] = riscv.REG_FS9
	register["FS10"] = riscv.REG_FS10
	register["FS11"] = riscv.REG_FS11
	register["FT8"] = riscv.REG_FT8
	register["FT9"] = riscv.REG_FT9
	register["FT10"] = riscv.REG_FT10
	register["FT11"] = riscv.REG_FT11

	// Pseudo-registers.
	register["SB"] = RSB
	register["FP"] = RFP
	register["PC"] = RPC

	VFADDVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
	VFSUBVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
	VFSUBVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
	VFRSUBVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
	VFWADDVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
	VFWADDVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"

	VFADDVV		V1, V2, V3			// d7912002
	VFADDVV		V1, V2, V0, V3			// d7912000
	VFADDVF		F10, V2, V3			// d7512502
	VFADDVF		F10, V2, V0, V3			// d7512500
	VFSUBVV		V1, V2, V3			// d791200a
	VFSUBVV		V1, V2, V0, V3			// d7912008
	VFSUBVF		F10, V2, V3			// d751250a
	VFSUBVF		F10, V2, V0, V3			// d7512508
	VFRSUBVF	F10, V2, V3			// d751259e
	VFRSUBVF	F10, V2, V0, V3			// d751259c

	CLWSP	20(SP), F10				// ERROR "expected integer register in rd position"
	CLWSP	22(SP), X10				// ERROR "must be a multiple of 4"
	CLDSP	24(X5), X10				// ERROR "rs2 must be SP/X2"
	CLDSP	24(SP), X0				// ERROR "cannot use register X0"
	CLDSP	24(SP), F10				// ERROR "expected integer register in rd position"
	CLDSP	28(SP), X10				// ERROR "must be a multiple of 8"
	CFLDSP	32(X5), F10				// ERROR "rs2 must be SP/X2"

    <glob pattern="*.fh8"/>
    <glob pattern="*.fh9"/>
    <glob pattern="*.fh10"/>
    <glob pattern="*.fh11"/>
    <glob pattern="*.fh12"/>
    <glob pattern="*.ft7"/>
    <glob pattern="*.ft8"/>
    <glob pattern="*.ft9"/>
    <glob pattern="*.ft10"/>
    <glob pattern="*.ft11"/>
    <glob pattern="*.ft12"/>
  </mime-type>

  <mime-type type="image/x-jbig2">

 * KIND, either express or implied.  See the License for the
 * specific language governing permissions and limitations
 * under the License.
 */
package org.apache.maven.project.inheritance.t10;

import java.io.File;
import java.util.Map;

import org.apache.maven.artifact.Artifact;
import org.apache.maven.project.MavenProject;
import org.apache.maven.project.inheritance.AbstractProjectInheritanceTestCase;

	FADDS	F0, F15                // b30a00f0
	FADD	F1, F14                // b31a00e1
	FSUBS	F2, F13                // b30b00d2
	FSUB	F3, F12                // b31b00c3
	FMULS	F4, F11                // b31700b4
	FMUL	F5, F10                // b31c00a5
	FDIVS	F6, F9                 // b30d0096
	FDIV	F7, F8                 // b31d0087
	FABS	F1, F2                 // b3100021
	FSQRTS	F3, F4                 // b3140043

	type UserMigrateColumn2 struct {
		ID  uint
		F1  string
		F2  string
		F3  string
		F4  string
		F5  string
		F6  string
		F7  string
		F8  string
		F9  string
		F10 string
		F11 string
		F12 string
		F13 string
		F14 string
		F15 string
		F16 string
		F17 string
		F18 string
		F19 string
		F20 string
		F21 string
		F22 string
		F23 string

	FMOVS	F1, 1(R2) // 411000bc
	FMOVS	F1, 4(R2) // 410400bd
	FMOVS	F20, (R0) // 140000bd
	FMOVD	F1, 1(R2) // 411000fc
	FMOVD	F1, 8(R2) // 410400fd
	FMOVD	F20, (R2) // 540000fd
	FMOVQ	F0, 32(R5)// a008803d
	FMOVQ	F10, 65520(R10) // 4afdbf3d
	FMOVQ	F11, 64(RSP)    // eb13803d
	FMOVQ	F11, 8(R20)     // 8b82803c
	FMOVQ	F11, 4(R20)     // 8b42803c

	MOVB	1(R1), R2 // 22048039
	MOVH	1(R1), R2 // 22108078