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Results 1 - 6 of 6 for X12 (0.04 sec)
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src/cmd/asm/internal/asm/testdata/riscv64.s
VSETVLI X10, E32, MF8, TA, MA, X12 // 5776550d VSETVLI X10, E32, MF4, TA, MA, X12 // 5776650d VSETVLI X10, E32, MF2, TA, MA, X12 // 5776750d VSETVLI X10, E32, M1, TA, MA, X12 // 5776050d VSETVLI $15, E32, M1, TA, MA, X12 // 57f607cd VSETIVLI $0, E32, M1, TA, MA, X12 // 577600cd VSETIVLI $15, E32, M1, TA, MA, X12 // 57f607cd VSETIVLI $31, E32, M1, TA, MA, X12 // 57f60fcd VSETVL X10, X11, X12 // 57f6a580
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed May 21 14:19:19 UTC 2025 - 49.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
VGATHERQPS X2, (BP)(Y7*2), X1 // c4e26d934c7d00 VGATHERQPS X12, (R13)(X14*2), X11 // c40219935c7500 VGATHERQPS X12, (R13)(Y14*2), X11 // c4021d935c7500 VGATHERQPS X2, (BP)(X7*2), X1 // c4e269934c7d00 VGATHERQPS X2, (BP)(Y7*2), X1 // c4e26d934c7d00 VGATHERQPS X12, (R13)(X14*2), X11 // c40219935c7500 VGATHERQPS X12, (R13)(Y14*2), X11 // c4021d935c7500
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu Feb 20 11:20:03 UTC 2025 - 57.7K bytes - Viewed (0) -
lib/fips140/v1.0.0.zip
MOVOU 80(DI), X12 PCLMULQDQ $0x00, X2, X12 PXOR X12, X10 MOVOU 96(DI), X12 MOVOU X12, X13 PCLMULQDQ $0x00, X3, X12 PXOR X12, X8 PCLMULQDQ $0x11, X3, X13 PXOR X13, X9 PSHUFD $0x4e, X3, X12 PXOR X12, X3 MOVOU 112(DI), X12 PCLMULQDQ $0x00, X3, X12 PXOR X12, X10 MOVOU 128(DI), X12 MOVOU X12, X13 PCLMULQDQ $0x00, X4, X12 PXOR X12, X8 PCLMULQDQ $0x11, X4, X13 PXOR X13, X9 PSHUFD $0x4e, X4, X12 PXOR X12, X4 MOVOU 144(DI), X12 PCLMULQDQ $0x00, X4, X12 PXOR X12, X10 MOVOU 160(DI), X12 MOVOU X12, X13 PCLMULQDQ...
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Jan 29 15:10:35 UTC 2025 - 635K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64validation.s
// // "V" Standard Extension for Vector Operations, Version 1.0 // VSETVLI $32, E16, M1, TU, MU, X12 // ERROR "must be in range [0, 31] (5 bits)" VSETVLI $-1, E32, M2, TA, MA, X12 // ERROR "must be in range [0, 31] (5 bits)" VSETVL X10, X11 // ERROR "expected integer register in rs1 position" VLE8V (X10), X10 // ERROR "expected vector register in vd position"
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed May 21 14:19:19 UTC 2025 - 31.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64error.s
MOVWU X5, (X6) // ERROR "unsupported unsigned store" MOVF F0, F1, F2 // ERROR "illegal MOV instruction" MOVD F0, F1, F2 // ERROR "illegal MOV instruction" MOV X10, X11, X12 // ERROR "illegal MOV instruction" MOVW X10, X11, X12 // ERROR "illegal MOV instruction" RORI $64, X5, X6 // ERROR "immediate out of range 0 to 63" SLLI $64, X5, X6 // ERROR "immediate out of range 0 to 63"
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu May 08 08:53:43 UTC 2025 - 24.8K bytes - Viewed (0) -
android/guava-tests/benchmark/com/google/common/base/EnumsBenchmark.java
X0, X1, X2 } private enum MediumEnum { X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29,
Registered: Fri Sep 05 12:43:10 UTC 2025 - Last Modified: Thu Dec 19 18:03:30 UTC 2024 - 29.4K bytes - Viewed (0)