Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 3 of 3 for VLSE8V (0.28 sec)

  1. src/cmd/asm/internal/asm/testdata/riscv64validation.s

    	VSE8V		V3, (V1)			// ERROR "expected integer register in rd position"
    	VLSE8V		(X10), V3			// ERROR "expected integer register in rs2 position"
    	VLSE8V		(X10), X10, X11			// ERROR "expected vector register in vd position"
    	VLSE8V		(V1), X10, V3			// ERROR "expected integer register in rs1 position"
    	VLSE8V		(X10), V1, V0, V3		// ERROR "expected integer register in rs2 position"
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed May 21 14:19:19 UTC 2025
    - 31.6K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/riscv64.s

    	VSE64V		V3, (X10)			// a7710502
    	VSE64V		V3, V0, (X10)			// a7710500
    	VLMV		(X10), V3			// 8701b502
    	VSMV		V3, (X10)			// a701b502
    
    	// 31.7.5: Vector Strided Instructions
    	VLSE8V		(X10), X11, V3			// 8701b50a
    	VLSE8V		(X10), X11, V0, V3		// 8701b508
    	VLSE16V		(X10), X11, V3			// 8751b50a
    	VLSE16V		(X10), X11, V0, V3		// 8751b508
    	VLSE32V		(X10), X11, V3			// 8761b50a
    	VLSE32V		(X10), X11, V0, V3		// 8761b508
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed May 21 14:19:19 UTC 2025
    - 49.1K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/riscv64error.s

    	//
    	VSETIVLI	X10, E32, M2, TA, MA, X12	// ERROR "expected immediate value"
    	VLE8V		(X10), V1, V3			// ERROR "invalid vector mask register"
    	VSE8V		V3, V1, (X10)			// ERROR "invalid vector mask register"
    	VLSE8V		(X10), X10, V1, V3		// ERROR "invalid vector mask register"
    	VSSE8V		V3, X11, V1, (X10)		// ERROR "invalid vector mask register"
    	VLUXEI8V	(X10), V2, V1, V3		// ERROR "invalid vector mask register"
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Thu May 08 08:53:43 UTC 2025
    - 24.8K bytes
    - Viewed (0)
Back to top