VSETVLI		$-1, E32, M2, TA, MA, X12	// ERROR "must be in range [0, 31] (5 bits)"
	VSETVL		X10, X11			// ERROR "expected integer register in rs1 position"
	VLE8V		(X10), X10			// ERROR "expected vector register in vd position"
	VLE8V		(V1), V3			// ERROR "expected integer register in rs1 position"
	VLE8FFV		(X10), X10			// ERROR "expected vector register in vd position"

	FENCE.TSO	R, R				// ERROR "FENCE.TSO must not have operands"

	//
	// "V" Standard Extension for Vector Operations, Version 1.0
	//
	VSETIVLI	X10, E32, M2, TA, MA, X12	// ERROR "expected immediate value"
	VLE8V		(X10), V1, V3			// ERROR "invalid vector mask register"
	VLE8FFV		(X10), V1, V3			// ERROR "invalid vector mask register"
	VSE8V		V3, V1, (X10)			// ERROR "invalid vector mask register"

	VSETIVLI $15, E32, M1, TA, MA, X12		// 57f607cd
	VSETIVLI $31, E32, M1, TA, MA, X12		// 57f60fcd
	VSETVL	X10, X11, X12				// 57f6a580

	// 31.7.4: Vector Unit-Stride Instructions
	VLE8V		(X10), V3			// 87010502
	VLE8V		(X10), V0, V3			// 87010500
	VLE16V		(X10), V3			// 87510502
	VLE16V		(X10), V0, V3			// 87510500
	VLE32V		(X10), V3			// 87610502
	VLE32V		(X10), V0, V3			// 87610500
	VLE64V		(X10), V3			// 87710502