Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 6 of 6 for S4 (0.01 sec)

  1. src/cmd/asm/internal/asm/testdata/arm64.s

    	DMB	$1
    	SVC
    
    // encryption
    	SHA256H	V9.S4, V3, V2                   // 6240095e
    	SHA256H2	V9.S4, V4, V3           // 8350095e
    	SHA256SU0	V8.S4, V7.S4            // 0729285e
    	SHA256SU1	V6.S4, V5.S4, V7.S4     // a760065e
    	SHA1SU0	V11.S4, V8.S4, V6.S4            // 06310b5e
    	SHA1SU1	V5.S4, V1.S4                    // a118285e
    	SHA1C	V1.S4, V2, V3                   // 4300015e
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Jul 24 18:45:14 UTC 2024
    - 95.2K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/arm64error.s

    	VST1.P	[V4.S4,V5.S4], 48(R1)                            // ERROR "invalid post-increment offset"
    	VST1.P	[V4.S4], 8(R1)                                   // ERROR "invalid post-increment offset"
    	VLD1.P	32(R1), [V8.S4, V9.S4, V10.S4]                   // ERROR "invalid post-increment offset"
    	VLD1.P	48(R1), [V7.S4, V8.S4, V9.S4, V10.S4]            // ERROR "invalid post-increment offset"
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 37.8K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/parse.go

    	}
    }
    
    // registerList parses an ARM or ARM64 register list expression, a list of
    // registers in []. There may be comma-separated ranges or individual
    // registers, as in [R1,R3-R5] or [V1.S4, V2.S4, V3.S4, V4.S4].
    // For ARM, only R0 through R15 may appear.
    // For ARM64, V0 through V31 with arrangement may appear.
    //
    // For 386/AMD64 register list specifies 4VNNIW-style multi-source operand.
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Sep 04 18:16:59 UTC 2024
    - 36.9K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/arch/arch.go

    	register["A4"] = riscv.REG_A4
    	register["A5"] = riscv.REG_A5
    	register["A6"] = riscv.REG_A6
    	register["A7"] = riscv.REG_A7
    	register["S2"] = riscv.REG_S2
    	register["S3"] = riscv.REG_S3
    	register["S4"] = riscv.REG_S4
    	register["S5"] = riscv.REG_S5
    	register["S6"] = riscv.REG_S6
    	register["S7"] = riscv.REG_S7
    	register["S8"] = riscv.REG_S8
    	register["S9"] = riscv.REG_S9
    	register["S10"] = riscv.REG_S10
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Thu Oct 24 12:32:56 UTC 2024
    - 21.5K bytes
    - Viewed (0)
  5. doc/go1.17_spec.html

    s2 := append(s1, 3, 5, 7)          // append multiple elements    s2 == []int{0, 0, 2, 3, 5, 7}
    s3 := append(s2, s0...)            // append a slice              s3 == []int{0, 0, 2, 3, 5, 7, 0, 0}
    s4 := append(s3[3:6], s3[2:]...)   // append overlapping slice    s4 == []int{3, 5, 7, 2, 3, 5, 7, 0, 0}
    
    var t []interface{}
    t = append(t, 42, 3.1415, "foo")   //                             t == []interface{}{42, 3.1415, "foo"}
    
    var b []byte
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Thu Oct 10 18:25:45 UTC 2024
    - 211.6K bytes
    - Viewed (0)
  6. doc/go_spec.html

    s2 := append(s1, 3, 5, 7)          // append multiple elements    s2 is []int{0, 0, 2, 3, 5, 7}
    s3 := append(s2, s0...)            // append a slice              s3 is []int{0, 0, 2, 3, 5, 7, 0, 0}
    s4 := append(s3[3:6], s3[2:]...)   // append overlapping slice    s4 is []int{3, 5, 7, 2, 3, 5, 7, 0, 0}
    
    var t []interface{}
    t = append(t, 42, 3.1415, "foo")   //                             t is []interface{}{42, 3.1415, "foo"}
    
    var b []byte
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Oct 02 00:58:01 UTC 2024
    - 282.5K bytes
    - Viewed (0)
Back to top