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Results 1 - 10 of 21 for MOVBload (0.39 sec)

  1. src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules

    // don't extend after proper load
    (MOVBreg  x:(MOVBload  _ _)) => (MOVDreg x)
    (MOVBUreg x:(MOVBUload _ _)) => (MOVDreg x)
    (MOVHreg  x:(MOVBload  _ _)) => (MOVDreg x)
    (MOVHreg  x:(MOVBUload _ _)) => (MOVDreg x)
    (MOVHreg  x:(MOVHload  _ _)) => (MOVDreg x)
    (MOVHUreg x:(MOVBUload _ _)) => (MOVDreg x)
    (MOVHUreg x:(MOVHUload _ _)) => (MOVDreg x)
    (MOVWreg  x:(MOVBload  _ _)) => (MOVDreg x)
    (MOVWreg  x:(MOVBUload _ _)) => (MOVDreg x)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 4.1K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    	(MOVHstore [2] dst (MOVHload [2] src mem)
    		(MOVHstore dst (MOVHload src mem) mem))
    (Move [4] dst src mem) =>
    	(MOVBstore [3] dst (MOVBload [3] src mem)
    		(MOVBstore [2] dst (MOVBload [2] src mem)
    			(MOVBstore [1] dst (MOVBload [1] src mem)
    				(MOVBstore dst (MOVBload src mem) mem))))
    (Move [8] {t} dst src mem) && t.Alignment()%8 == 0 =>
    	(MOVDstore dst (MOVDload src mem) mem)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/MIPS64.rules

    	(MOVHstore [2] dst (MOVHload [2] src mem)
    		(MOVHstore dst (MOVHload src mem) mem))
    (Move [4] dst src mem) =>
    	(MOVBstore [3] dst (MOVBload [3] src mem)
    		(MOVBstore [2] dst (MOVBload [2] src mem)
    			(MOVBstore [1] dst (MOVBload [1] src mem)
    				(MOVBstore dst (MOVBload src mem) mem))))
    (Move [8] {t} dst src mem) && t.Alignment()%8 == 0 =>
    	(MOVVstore dst (MOVVload src mem) mem)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 41.9K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/LOONG64.rules

    	(MOVHstore [2] dst (MOVHload [2] src mem)
    		(MOVHstore dst (MOVHload src mem) mem))
    (Move [4] dst src mem) =>
    	(MOVBstore [3] dst (MOVBload [3] src mem)
    		(MOVBstore [2] dst (MOVBload [2] src mem)
    			(MOVBstore [1] dst (MOVBload [1] src mem)
    				(MOVBstore dst (MOVBload src mem) mem))))
    (Move [8] {t} dst src mem) && t.Alignment()%8 == 0 =>
    	(MOVVstore dst (MOVVload src mem) mem)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/rewriteARM64latelower.go

    			break
    		}
    		v.reset(OpARM64MOVDreg)
    		v.AddArg(x)
    		return true
    	}
    	return false
    }
    func rewriteValueARM64latelower_OpARM64MOVBreg(v *Value) bool {
    	v_0 := v.Args[0]
    	// match: (MOVBreg x:(MOVBload _ _))
    	// result: (MOVDreg x)
    	for {
    		x := v_0
    		if x.Op != OpARM64MOVBload {
    			break
    		}
    		v.reset(OpARM64MOVDreg)
    		v.AddArg(x)
    		return true
    	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 19.3K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/AMD64.rules

    (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
    (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
    (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 93.9K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/ARM.rules

    (SUBconst [off1] (MOVWaddr [off2] {sym} ptr)) => (MOVWaddr [off2-off1] {sym} ptr)
    
    // fold address into load/store
    (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) => (MOVBload [off1+off2] {sym} ptr mem)
    (MOVBload [off1] {sym} (SUBconst [off2] ptr) mem) => (MOVBload [off1-off2] {sym} ptr mem)
    (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) => (MOVBUload [off1+off2] {sym} ptr mem)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 90.1K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/rewriteLOONG64.go

    		v1.AddArg3(dst, v2, mem)
    		v.AddArg3(dst, v0, v1)
    		return true
    	}
    	// match: (Move [4] dst src mem)
    	// result: (MOVBstore [3] dst (MOVBload [3] src mem) (MOVBstore [2] dst (MOVBload [2] src mem) (MOVBstore [1] dst (MOVBload [1] src mem) (MOVBstore dst (MOVBload src mem) mem))))
    	for {
    		if auxIntToInt64(v.AuxInt) != 4 {
    			break
    		}
    		dst := v_0
    		src := v_1
    		mem := v_2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 195.8K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/_gen/ARM64.rules

    // Do not fold global variable access in -dynlink mode, where it will
    // be rewritten to use the GOT via REGTMP, which currently cannot handle
    // large offset.
    (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
    	&& (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
    	(MOVBload [off1+int32(off2)] {sym} ptr mem)
    (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/rewriteRISCV64.go

    		v1.AddArg3(dst, v2, mem)
    		v.AddArg3(dst, v0, v1)
    		return true
    	}
    	// match: (Move [4] dst src mem)
    	// result: (MOVBstore [3] dst (MOVBload [3] src mem) (MOVBstore [2] dst (MOVBload [2] src mem) (MOVBstore [1] dst (MOVBload [1] src mem) (MOVBstore dst (MOVBload src mem) mem))))
    	for {
    		if auxIntToInt64(v.AuxInt) != 4 {
    			break
    		}
    		dst := v_0
    		src := v_1
    		mem := v_2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 205.1K bytes
    - Viewed (0)
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