- Sort Score
- Result 10 results
- Languages All
Results 1 - 7 of 7 for MIPS (0.04 sec)
-
src/cmd/asm/internal/arch/arch.go
// Note that there is no list of names as there is for x86. for i := mips.REG_R0; i <= mips.REG_R31; i++ { register[obj.Rconv(i)] = int16(i) } for i := mips.REG_F0; i <= mips.REG_F31; i++ { register[obj.Rconv(i)] = int16(i) } for i := mips.REG_M0; i <= mips.REG_M31; i++ { register[obj.Rconv(i)] = int16(i) } for i := mips.REG_FCR0; i <= mips.REG_FCR31; i++ { register[obj.Rconv(i)] = int16(i) }
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Thu Oct 24 12:32:56 UTC 2024 - 21.5K bytes - Viewed (0) -
buildscripts/cross-compile.sh
## List of architectures and OS to test coss compilation. SUPPORTED_OSARCH="linux/ppc64le linux/mips64 linux/amd64 linux/arm64 linux/s390x darwin/arm64 darwin/amd64 freebsd/amd64 windows/amd64 linux/arm linux/386 netbsd/amd64 linux/mips openbsd/amd64" } function _build() { local osarch=$1 IFS=/ read -r -a arr <<<"$osarch" os="${arr[0]}" arch="${arr[1]}" package=$(go list -f '{{.ImportPath}}')
Registered: Sun Nov 03 19:28:11 UTC 2024 - Last Modified: Tue Dec 19 01:08:22 UTC 2023 - 958 bytes - Viewed (0) -
src/cmd/asm/internal/asm/endtoend_test.go
testErrors(t, "amd64", "amd64error") } func TestAMD64DynLinkErrors(t *testing.T) { testErrors(t, "amd64", "amd64dynlinkerror", "dynlink") } func TestMIPSEndToEnd(t *testing.T) { testEndToEnd(t, "mips", "mips") testEndToEnd(t, "mips64", "mips64") } func TestLOONG64Encoder(t *testing.T) { testEndToEnd(t, "loong64", "loong64enc1") testEndToEnd(t, "loong64", "loong64enc2")
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Thu Dec 07 18:42:59 UTC 2023 - 11.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/asm.go
reg, success := ppc64.ConstantToCRbit(c) if !success { p.errorf("invalid CR bit register number %d", c) } prog.Reg = reg } break } if p.arch.Family == sys.MIPS || p.arch.Family == sys.MIPS64 || p.arch.Family == sys.RISCV64 { // 3-operand jumps. // First two must be registers target = &a[2] prog.From = a[0] prog.Reg = p.getRegister(prog, op, &a[1]) break
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Mon Oct 21 14:11:44 UTC 2024 - 25.5K bytes - Viewed (0) -
doc/asm.html
<ul> <li> <code>(R5)(R6*1)</code>: The location at <code>R5</code> plus <code>R6</code>. It is a scaled mode as on the x86, but the only scale allowed is <code>1</code>. </li> </ul> <h3 id="mips">MIPS, MIPS64</h3> <p> General purpose registers are named <code>R0</code> through <code>R31</code>, floating point registers are <code>F0</code> through <code>F31</code>. </p> <p>
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Nov 28 19:15:27 UTC 2023 - 36.3K bytes - Viewed (0) -
tensorflow/BUILD
), visibility = ["//visibility:public"], ) config_setting( name = "android_mips", values = { "crosstool_top": "//external:android/crosstool", "cpu": "mips", }, visibility = ["//visibility:public"], ) config_setting( name = "android_mips64", values = { "crosstool_top": "//external:android/crosstool", "cpu": "mips64",
Registered: Tue Nov 05 12:39:12 UTC 2024 - Last Modified: Wed Oct 16 05:28:35 UTC 2024 - 53.5K bytes - Viewed (0) -
src/cmd/cgo/gcc.go
case "mips64", "mips64le": if gomips64 == "hardfloat" { return []string{"-mabi=64", "-mhard-float"} } else if gomips64 == "softfloat" { return []string{"-mabi=64", "-msoft-float"} } case "mips", "mipsle": if gomips == "hardfloat" { return []string{"-mabi=32", "-mfp32", "-mhard-float", "-mno-odd-spreg"} } else if gomips == "softfloat" { return []string{"-mabi=32", "-msoft-float"} }
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Sep 18 15:07:34 UTC 2024 - 97.1K bytes - Viewed (0)