- Sort Score
- Result 10 results
- Languages All
Results 1 - 4 of 4 for MFENCE (0.09 sec)
-
src/internal/runtime/atomic/atomic_386.s
// MOVQ and EMMS were introduced on the Pentium MMX. MOVQ val+4(FP), M0 MOVQ M0, (AX) EMMS // This is essentially a no-op, but it provides required memory fencing. // It can be replaced with MFENCE, but MFENCE was introduced only on the Pentium4 (SSE2). XORL AX, AX LOCK XADDL AX, (SP) RET // void ·Or8(byte volatile*, byte); TEXT ·Or8(SB), NOSPLIT, $0-5 MOVL ptr+0(FP), AX MOVB val+4(FP), BX
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 6.5K bytes - Viewed (0) -
src/runtime/asm_386.s
done: MOVL AX, ret_lo+0(FP) MOVL DX, ret_hi+4(FP) RET fences: // MFENCE is instruction stream serializing and flushes the // store buffers on AMD. The serialization semantics of LFENCE on AMD // are dependent on MSR C001_1029 and CPU generation. // LFENCE on Intel does wait for all previous instructions to have executed. // Intel recommends MFENCE;LFENCE in its manuals before RDTSC to have all
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 15 15:45:13 UTC 2024 - 43.1K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_riscv64.s
// // These four modes correspond to other well-known memory models on other CPUs. // On ARM, aq corresponds to a dmb ishst, aq+rl corresponds to a dmb ish. On // Intel, aq corresponds to an lfence, rl to an sfence, and aq+rl to an mfence // (or a lock prefix). // // Go's memory model requires that // - if a read happens after a write, the read must observe the write, and // that
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 7K bytes - Viewed (0) -
src/runtime/asm_amd64.s
SHLQ $32, DX ADDQ DX, AX MOVQ AX, ret+0(FP) RET fences: // MFENCE is instruction stream serializing and flushes the // store buffers on AMD. The serialization semantics of LFENCE on AMD // are dependent on MSR C001_1029 and CPU generation. // LFENCE on Intel does wait for all previous instructions to have executed. // Intel recommends MFENCE;LFENCE in its manuals before RDTSC to have all
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat May 11 20:38:24 UTC 2024 - 60.4K bytes - Viewed (0)