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src/cmd/compile/internal/ssa/_gen/AMD64.rules
(CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) && is32Bit(int64(off1)+int64(off2)) => (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) // We don't need the conditional move if we know the arg of BSF is not zero. (CMOVQEQ x _ (Select1 (BS(F|R)Q (ORQconst [c] _)))) && c != 0 => x // Extension is unnecessary for trailing zeros. (BSFQ (ORQconst <t> [1<<8] (MOVBQZX x))) => (BSFQ (ORQconst <t> [1<<8] x))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
fess-crawler/src/main/resources/org/codelibs/fess/crawler/mime/tika-mimetypes.xml
<mime-type type="application/tve-trigger"/> <mime-type type="application/ulpfec"/> <mime-type type="application/vemmi"/> <mime-type type="application/vividence.scriptfile"/> <mime-type type="application/vnd.3gpp.bsf+xml"/> <mime-type type="application/vnd.3gpp.pic-bw-large"> <glob pattern="*.plb"/> </mime-type> <mime-type type="application/vnd.3gpp.pic-bw-small"> <glob pattern="*.psb"/> </mime-type>
Registered: Wed Jun 12 15:17:51 UTC 2024 - Last Modified: Thu Sep 21 06:46:43 UTC 2023 - 298.5K bytes - Viewed (0)