AND	$-65536, R1           // c01bffff0000
	AND	$1, R1                // c0a100000001b980001a
	ANDW	R1, R2                // 1421
	ANDW	R1, R2, R3            // b9f42031
	ANDW	$1, R1                // c01b00000001
	ANDW	$131071, R1           // a5160001
	ANDW	$65536, R1            // c01b00010000
	ANDW	$-2, R1               // a517fffe
	OR	R1, R2                // b9810021
	OR	R1, R2, R3            // b9e62031

	MOVW	R6, R14
	MOVW	R7, R15

	MOVW	(0*4)(R1), R8
	MOVW	R7, R9

#define ROUND1(a, b, c, d, index, const, shift) \
	ADDW	$const, a; \
	ADDW	R8, a; \
	MOVW	(index*4)(R1), R8; \
	EORW	c, R9; \
	ANDW	b, R9; \
	EORW	d, R9; \
	ADDW	R9, a; \
	RORW	$(32-shift), a; \
	MOVW	c, R9; \
	ADDW	b, a

	ROUND1(R4,R5,R6,R7, 1,0xd76aa478, 7);
	ROUND1(R7,R4,R5,R6, 2,0xe8c7b756,12);
	ROUND1(R6,R7,R4,R5, 3,0x242070db,17);

	// containing v to OR with the entire word atomically.
	MOVD	$(3<<3), R5
	RXSBG	$59, $60, $3, R3, R5 // R5 = 24 - ((addr % 4) * 8) = ((addr & 3) << 3) ^ (3 << 3)
	ANDW	$~3, R3              // R3 = floor(addr, 4) = addr &^ 3
	SLW	R5, R4               // R4 = uint32(v) << R5
	LAO	R4, R6, 0(R3)        // R6 = *R3; *R3 |= R4; (atomic)
	RET

// func And8(addr *uint8, v uint8)

	"MOVHBR",
	"MOVHZ",
	"MOVW",
	"MOVWZ",
	"MOVD",
	"MOVDBR",
	"MOVDEQ",
	"MOVDGE",
	"MOVDGT",
	"MOVDLE",
	"MOVDLT",
	"MOVDNE",
	"LOCR",
	"LOCGR",
	"FLOGR",
	"POPCNT",
	"AND",
	"ANDW",
	"OR",
	"ORW",
	"XOR",
	"XORW",
	"SLW",
	"SLD",
	"SRW",
	"SRAW",
	"SRD",
	"SRAD",
	"RLL",
	"RLLG",
	"RNSBG",
	"RXSBG",
	"ROSBG",
	"RNSBGT",
	"RXSBGT",
	"ROSBGT",

  && c < 0
  => (ANDconst [c] x)
(AND x (MOVDconst [c]))
  && is32Bit(c)
  && c >= 0
  => (MOVWZreg (ANDWconst <typ.UInt32> [int32(c)] x))

(ANDW x (MOVDconst [c])) => (ANDWconst [int32(c)] x)

((AND|ANDW)const [c] ((AND|ANDW)const [d] x)) => ((AND|ANDW)const [c&d] x)

((OR|XOR) x (MOVDconst [c])) && isU32Bit(c) => ((OR|XOR)const [c] x)
((OR|XOR)W x (MOVDconst [c])) => ((OR|XOR)Wconst [int32(c)] x)

	EOR	$(1<<63), R1                        // EOR	$-9223372036854775808, R1       // 210041d2
	EOR	$(1<<63-1), R1                      // EOR	$9223372036854775807, R1        // 21f840d2
	ANDW	$0x3ff00000, R2                     // ANDW	$1072693248, R2                 // 42240c12
	BICW	$0x3ff00000, R2                     // BICW	$1072693248, R2                 // 42540212

	ADDSW R7->22, R14, R13                     // cd59872b
	ADDS R14>>7, ZR, R4                        // e41f4eab
	AND $-9223372036854775808, R1, R1          // 21004192
	ANDW $4026540031, R29, R2                  // a2430412
	AND $34903429696192636, R12, R19           // 93910e92
	ANDW R9@>7, R19, R26                       // 7a1ec90a
	AND R9@>7, R19, R26                        // 7a1ec98a
	TSTW $2863311530, R24                      // 1ff30172

	ADD	$0x3fffffffc000, R27, R5                         // ERROR "cannot use REGTMP as source"
	AND	$0x22220000, R27, R4                             // ERROR "cannot use REGTMP as source"
	ANDW	$0x6006000060060, R27, R5                        // ERROR "cannot use REGTMP as source"
	STP	(R3, R4), 0x1234567(R27)                         // ERROR "REGTMP used in large offset store"

			v.AuxInt = int32ToAuxInt(int32(c))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (ANDW x x)
	// result: x
	for {
		x := v_0
		if x != v_1 {
			break
		}
		v.copyOf(x)
		return true
	}
	// match: (ANDW <t> x g:(MOVWload [off] {sym} ptr mem))
	// cond: ptr.Op != OpSB && is20Bit(int64(off)) && canMergeLoadClobber(v, g, x) && clobber(g)

				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "ANDW",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		asm:          s390x.AANDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14