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Results 1 - 8 of 8 for AMULW (0.08 sec)
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src/cmd/internal/obj/loong64/a.out.go
AMOVDW AMOVF AMOVFD AMOVFW AMOVH AMOVHU AMOVW AMOVWD AMOVWF AMOVWL AMOVWR AMUL AMULD AMULF AMULU AMULH AMULHU AMULW ANEGD ANEGF ANEGW ANEGV ANOOP // hardware nop ANOR AOR AREM AREMU ARFE ASC ASCV ASGT ASGTU ASLL ASQRTD
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 5.7K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/cpu.go
ASRAIW AADDW ASLLW ASRLW ASUBW ASRAW // 5.3: Load and Store Instructions (RV64I) ALD ASD // 7.1: Multiplication Operations AMUL AMULH AMULHU AMULHSU AMULW ADIV ADIVU AREM AREMU ADIVW ADIVUW AREMW AREMUW // 8.2: Load-Reserved/Store-Conditional Instructions ALRD ASCD ALRW ASCW
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.1K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/inst.go
return &inst{0x33, 0x0, 0x0, 32, 0x1} case AMULH: return &inst{0x33, 0x1, 0x0, 32, 0x1} case AMULHSU: return &inst{0x33, 0x2, 0x0, 32, 0x1} case AMULHU: return &inst{0x33, 0x3, 0x0, 32, 0x1} case AMULW: return &inst{0x3b, 0x0, 0x0, 32, 0x1} case AOR: return &inst{0x33, 0x6, 0x0, 0, 0x0} case AORCB: return &inst{0x13, 0x5, 0x7, 647, 0x14} case AORI: return &inst{0x13, 0x6, 0x0, 0, 0x0}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.9K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/a.out.go
AMOVK AMOVKW AMOVN AMOVNW AMOVP AMOVPD AMOVPQ AMOVPS AMOVPSW AMOVPW AMOVW AMOVWU AMOVZ AMOVZW AMRS AMSR AMSUB AMSUBW AMUL AMULW AMVN AMVNW ANEG ANEGS ANEGSW ANEGW ANGC ANGCS ANGCSW ANGCW ANOOP AORN AORNW AORR AORRW APRFM APRFUM ARBIT ARBITW AREM
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 18 17:56:30 UTC 2023 - 18.1K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
case AADDI, ASLTI, ASLTIU, AANDI, AORI, AXORI, ASLLI, ASRLI, ASRAI, AADDIW, ASLLIW, ASRLIW, ASRAIW, AADDW, ASUBW, ASLLW, ASRLW, ASRAW, AADD, AAND, AOR, AXOR, ASLL, ASRL, ASUB, ASRA, AMUL, AMULH, AMULHU, AMULHSU, AMULW, ADIV, ADIVU, ADIVW, ADIVUW, AREM, AREMU, AREMW, AREMUW, AADDUW, ASH1ADD, ASH1ADDUW, ASH2ADD, ASH2ADDUW, ASH3ADD, ASH3ADDUW, ASLLIUW, AANDN, AORN, AXNOR, AMAX, AMAXU, AMIN, AMINU, AROL, AROLW, AROR, ARORW, ARORI, ARORIW,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/asm7.go
oprangeset(AUMADDL, t) oprangeset(AUMSUBL, t) case AREM: oprangeset(AREMW, t) oprangeset(AUREM, t) oprangeset(AUREMW, t) case AMUL: oprangeset(AMULW, t) oprangeset(AMNEG, t) oprangeset(AMNEGW, t) oprangeset(ASMNEGL, t) oprangeset(ASMULL, t) oprangeset(ASMULH, t) oprangeset(AUMNEGL, t) oprangeset(AUMULH, t)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 201.1K bytes - Viewed (0) -
src/cmd/internal/obj/x86/asm6.go
{AMULPD, yxm, Pe, opBytes{0x59}}, {AMULPS, yxm, Ym, opBytes{0x59}}, {AMULQ, ydivl, Pw, opBytes{0xf7, 04}}, {AMULSD, yxm, Pf2, opBytes{0x59}}, {AMULSS, yxm, Pf3, opBytes{0x59}}, {AMULW, ydivl, Pe, opBytes{0xf7, 04}}, {ANEGB, yscond, Pb, opBytes{0xf6, 03}}, {ANEGL, yscond, Px, opBytes{0xf7, 03}}, {ANEGQ, yscond, Pw, opBytes{0xf7, 03}}, {ANEGW, yscond, Pe, opBytes{0xf7, 03}},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 146.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, }, }, { name: "MULW", argLen: 2, commutative: true, asm: arm64.AMULW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)