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Results 1 - 10 of 11 for AMUL (0.09 sec)
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src/cmd/asm/internal/arch/loong64.go
} // IsLoong64MUL reports whether the op (as defined by an loong64.A* constant) is // one of the MUL/DIV/REM instructions that require special handling. func IsLoong64MUL(op obj.As) bool { switch op { case loong64.AMUL, loong64.AMULU, loong64.AMULV, loong64.AMULVU, loong64.ADIV, loong64.ADIVU, loong64.ADIVV, loong64.ADIVVU, loong64.AREM, loong64.AREMU, loong64.AREMV, loong64.AREMVU: return true } return false }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 2.1K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/a.out.go
ALUI AMOVB AMOVBU AMOVD AMOVDF AMOVDW AMOVF AMOVFD AMOVFW AMOVH AMOVHU AMOVW AMOVWD AMOVWF AMOVWL AMOVWR AMUL AMULD AMULF AMULU AMULH AMULHU AMULW ANEGD ANEGF ANEGW ANEGV ANOOP // hardware nop ANOR AOR AREM AREMU ARFE ASC
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 5.7K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/cpu.go
AADDIW ASLLIW ASRLIW ASRAIW AADDW ASLLW ASRLW ASUBW ASRAW // 5.3: Load and Store Instructions (RV64I) ALD ASD // 7.1: Multiplication Operations AMUL AMULH AMULHU AMULHSU AMULW ADIV ADIVU AREM AREMU ADIVW ADIVUW AREMW AREMUW // 8.2: Load-Reserved/Store-Conditional Instructions ALRD ASCD ALRW
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.1K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/inst.go
return &inst{0x33, 0x7, 0x0, 160, 0x5} case AMIN: return &inst{0x33, 0x4, 0x0, 160, 0x5} case AMINU: return &inst{0x33, 0x5, 0x0, 160, 0x5} case AMRET: return &inst{0x73, 0x0, 0x2, 770, 0x18} case AMUL: return &inst{0x33, 0x0, 0x0, 32, 0x1} case AMULH: return &inst{0x33, 0x1, 0x0, 32, 0x1} case AMULHSU: return &inst{0x33, 0x2, 0x0, 32, 0x1} case AMULHU: return &inst{0x33, 0x3, 0x0, 32, 0x1}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.9K bytes - Viewed (0) -
src/cmd/internal/obj/mips/asm0.go
{AMOVV, C_REG, C_NONE, C_HI, 21, 4, 0, sys.MIPS64, 0}, {AMOVW, C_REG, C_NONE, C_LO, 21, 4, 0, 0, 0}, {AMOVV, C_REG, C_NONE, C_LO, 21, 4, 0, sys.MIPS64, 0}, {AMUL, C_REG, C_REG, C_NONE, 22, 4, 0, 0, 0}, {AMUL, C_REG, C_REG, C_REG, 22, 4, 0, 0, 0}, {AMULV, C_REG, C_REG, C_NONE, 22, 4, 0, sys.MIPS64, 0}, {AADD, C_ADD0CON, C_REG, C_REG, 4, 4, 0, 0, 0}, {AADD, C_ADD0CON, C_NONE, C_REG, 4, 4, 0, 0, 0},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 17:46:09 UTC 2024 - 53.6K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/a.out.go
AMOVHU AMOVK AMOVKW AMOVN AMOVNW AMOVP AMOVPD AMOVPQ AMOVPS AMOVPSW AMOVPW AMOVW AMOVWU AMOVZ AMOVZW AMRS AMSR AMSUB AMSUBW AMUL AMULW AMVN AMVNW ANEG ANEGS ANEGSW ANEGW ANGC ANGCS ANGCSW ANGCW ANOOP AORN AORNW AORR AORRW APRFM APRFUM ARBIT ARBITW
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 18 17:56:30 UTC 2023 - 18.1K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/asm.go
{AMOVV, C_LCON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP}, {AMOVV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 59, 16, 0, NOTUSETMP}, {AMUL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, {AMUL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, {AMULV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, {AMULV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 61.8K bytes - Viewed (0) -
src/cmd/internal/obj/arm/asm5.go
{AMOVH, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0, 0}, {AMOVHS, C_REG, C_NONE, C_REG, 14, 8, 0, 0, 0, 0}, {AMOVHU, C_REG, C_NONE, C_REG, 14, 8, 0, 0, 0, 0}, {AMUL, C_REG, C_REG, C_REG, 15, 4, 0, 0, 0, C_SBIT}, {AMUL, C_REG, C_NONE, C_REG, 15, 4, 0, 0, 0, C_SBIT}, {ADIV, C_REG, C_REG, C_REG, 16, 4, 0, 0, 0, 0}, {ADIV, C_REG, C_NONE, C_REG, 16, 4, 0, 0, 0, 0}, {ADIVHW, C_REG, C_REG, C_REG, 105, 4, 0, 0, 0, 0},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 79.4K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
switch p.As { case AADDI, ASLTI, ASLTIU, AANDI, AORI, AXORI, ASLLI, ASRLI, ASRAI, AADDIW, ASLLIW, ASRLIW, ASRAIW, AADDW, ASUBW, ASLLW, ASRLW, ASRAW, AADD, AAND, AOR, AXOR, ASLL, ASRL, ASUB, ASRA, AMUL, AMULH, AMULHU, AMULHSU, AMULW, ADIV, ADIVU, ADIVW, ADIVUW, AREM, AREMU, AREMW, AREMUW, AADDUW, ASH1ADD, ASH1ADDUW, ASH2ADD, ASH2ADDUW, ASH3ADD, ASH3ADDUW, ASLLIUW,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/asm7.go
{ACMP, C_EXTREG, C_RSP, C_NONE, C_NONE, C_NONE, 27, 4, 0, 0, 0}, {AADD, C_ZREG, C_ZREG, C_NONE, C_ZREG, C_NONE, 1, 4, 0, 0, 0}, {AADD, C_ZREG, C_NONE, C_NONE, C_ZREG, C_NONE, 1, 4, 0, 0, 0}, {AMUL, C_ZREG, C_ZREG, C_NONE, C_ZREG, C_NONE, 15, 4, 0, 0, 0}, {AMUL, C_ZREG, C_NONE, C_NONE, C_ZREG, C_NONE, 15, 4, 0, 0, 0}, {AMADD, C_ZREG, C_ZREG, C_ZREG, C_ZREG, C_NONE, 15, 4, 0, 0, 0}, {AREM, C_ZREG, C_ZREG, C_NONE, C_ZREG, C_NONE, 16, 8, 0, 0, 0},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 201.1K bytes - Viewed (0)