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Results 1 - 10 of 15 for AMUL (0.04 sec)

  1. src/cmd/asm/internal/arch/mips.go

    }
    
    // IsMIPSMUL reports whether the op (as defined by an mips.A* constant) is
    // one of the MUL/DIV/REM/MADD/MSUB instructions that require special handling.
    func IsMIPSMUL(op obj.As) bool {
    	switch op {
    	case mips.AMUL, mips.AMULU, mips.AMULV, mips.AMULVU,
    		mips.ADIV, mips.ADIVU, mips.ADIVV, mips.ADIVVU,
    		mips.AREM, mips.AREMU, mips.AREMV, mips.AREMVU,
    		mips.AMADD, mips.AMSUB:
    		return true
    	}
    	return false
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 04 19:06:44 UTC 2020
    - 1.7K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/arch/loong64.go

    }
    
    // IsLoong64MUL reports whether the op (as defined by an loong64.A* constant) is
    // one of the MUL/DIV/REM instructions that require special handling.
    func IsLoong64MUL(op obj.As) bool {
    	switch op {
    	case loong64.AMUL, loong64.AMULU, loong64.AMULV, loong64.AMULVU,
    		loong64.ADIV, loong64.ADIVU, loong64.ADIVV, loong64.ADIVVU,
    		loong64.AREM, loong64.AREMU, loong64.AREMV, loong64.AREMVU:
    		return true
    	}
    	return false
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 2.1K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/loong64/a.out.go

    	ALUI
    
    	AMOVB
    	AMOVBU
    
    	AMOVD
    	AMOVDF
    	AMOVDW
    	AMOVF
    	AMOVFD
    	AMOVFW
    
    	AMOVH
    	AMOVHU
    	AMOVW
    
    	AMOVWD
    	AMOVWF
    
    	AMOVWL
    	AMOVWR
    
    	AMUL
    	AMULD
    	AMULF
    	AMULU
    	AMULH
    	AMULHU
    	AMULW
    	ANEGD
    	ANEGF
    
    	ANEGW
    	ANEGV
    
    	ANOOP // hardware nop
    	ANOR
    	AOR
    	AREM
    	AREMU
    
    	ARFE
    
    	ASC
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 5.7K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/mips/a.out.go

    	ALL
    	ALLV
    	ALUI
    	AMADD
    	AMOVB
    	AMOVBU
    	AMOVD
    	AMOVDF
    	AMOVDW
    	AMOVF
    	AMOVFD
    	AMOVFW
    	AMOVH
    	AMOVHU
    	AMOVW
    	AMOVWD
    	AMOVWF
    	AMOVWL
    	AMOVWR
    	AMSUB
    	AMUL
    	AMULD
    	AMULF
    	AMULU
    	AMULW
    	ANEGD
    	ANEGF
    	ANEGW
    	ANEGV
    	ANOOP // hardware nop
    	ANOR
    	AOR
    	AREM
    	AREMU
    	ARFE
    	AROTR
    	AROTRV
    	ASC
    	ASCV
    	ASEB
    	ASEH
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 7.6K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/arm/a.out.go

    	AFNMULAD
    	AFMULSF
    	AFMULSD
    	AFNMULSF
    	AFNMULSD
    	ADIVF
    	ADIVD
    	ASQRTF
    	ASQRTD
    	AABSF
    	AABSD
    	ANEGF
    	ANEGD
    
    	ASRL
    	ASRA
    	ASLL
    	AMULU
    	ADIVU
    	AMUL
    	AMMUL
    	ADIV
    	AMOD
    	AMODU
    	ADIVHW
    	ADIVUHW
    
    	AMOVB
    	AMOVBS
    	AMOVBU
    	AMOVH
    	AMOVHS
    	AMOVHU
    	AMOVW
    	AMOVM
    	ASWPBU
    	ASWPW
    
    	ARFE
    	ASWI
    	AMULA
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 05 16:22:12 UTC 2021
    - 7K bytes
    - Viewed (0)
  6. src/cmd/internal/obj/riscv/cpu.go

    	AADDIW
    	ASLLIW
    	ASRLIW
    	ASRAIW
    	AADDW
    	ASLLW
    	ASRLW
    	ASUBW
    	ASRAW
    
    	// 5.3: Load and Store Instructions (RV64I)
    	ALD
    	ASD
    
    	// 7.1: Multiplication Operations
    	AMUL
    	AMULH
    	AMULHU
    	AMULHSU
    	AMULW
    	ADIV
    	ADIVU
    	AREM
    	AREMU
    	ADIVW
    	ADIVUW
    	AREMW
    	AREMUW
    
    	// 8.2: Load-Reserved/Store-Conditional Instructions
    	ALRD
    	ASCD
    	ALRW
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.1K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/riscv/inst.go

    		return &inst{0x33, 0x7, 0x0, 160, 0x5}
    	case AMIN:
    		return &inst{0x33, 0x4, 0x0, 160, 0x5}
    	case AMINU:
    		return &inst{0x33, 0x5, 0x0, 160, 0x5}
    	case AMRET:
    		return &inst{0x73, 0x0, 0x2, 770, 0x18}
    	case AMUL:
    		return &inst{0x33, 0x0, 0x0, 32, 0x1}
    	case AMULH:
    		return &inst{0x33, 0x1, 0x0, 32, 0x1}
    	case AMULHSU:
    		return &inst{0x33, 0x2, 0x0, 32, 0x1}
    	case AMULHU:
    		return &inst{0x33, 0x3, 0x0, 32, 0x1}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.9K bytes
    - Viewed (0)
  8. src/cmd/internal/obj/mips/asm0.go

    	{AMOVV, C_REG, C_NONE, C_HI, 21, 4, 0, sys.MIPS64, 0},
    	{AMOVW, C_REG, C_NONE, C_LO, 21, 4, 0, 0, 0},
    	{AMOVV, C_REG, C_NONE, C_LO, 21, 4, 0, sys.MIPS64, 0},
    
    	{AMUL, C_REG, C_REG, C_NONE, 22, 4, 0, 0, 0},
    	{AMUL, C_REG, C_REG, C_REG, 22, 4, 0, 0, 0},
    	{AMULV, C_REG, C_REG, C_NONE, 22, 4, 0, sys.MIPS64, 0},
    
    	{AADD, C_ADD0CON, C_REG, C_REG, 4, 4, 0, 0, 0},
    	{AADD, C_ADD0CON, C_NONE, C_REG, 4, 4, 0, 0, 0},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 17:46:09 UTC 2024
    - 53.6K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/arm64/a.out.go

    	AMOVHU
    	AMOVK
    	AMOVKW
    	AMOVN
    	AMOVNW
    	AMOVP
    	AMOVPD
    	AMOVPQ
    	AMOVPS
    	AMOVPSW
    	AMOVPW
    	AMOVW
    	AMOVWU
    	AMOVZ
    	AMOVZW
    	AMRS
    	AMSR
    	AMSUB
    	AMSUBW
    	AMUL
    	AMULW
    	AMVN
    	AMVNW
    	ANEG
    	ANEGS
    	ANEGSW
    	ANEGW
    	ANGC
    	ANGCS
    	ANGCSW
    	ANGCW
    	ANOOP
    	AORN
    	AORNW
    	AORR
    	AORRW
    	APRFM
    	APRFUM
    	ARBIT
    	ARBITW
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 18 17:56:30 UTC 2023
    - 18.1K bytes
    - Viewed (0)
  10. src/cmd/internal/obj/loong64/asm.go

    	{AMOVV, C_LCON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
    	{AMOVV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 59, 16, 0, NOTUSETMP},
    
    	{AMUL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    	{AMUL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    	{AMULV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    	{AMULV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 61.8K bytes
    - Viewed (0)
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