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Results 1 - 5 of 5 for ADDW (0.4 sec)

  1. src/cmd/asm/internal/asm/testdata/s390x.s

    	ADDC	$1, R1, R2            // ec21000100db
    	ADDC	$-1, R1, R2           // ec21ffff00db
    	ADDC	R1, R2, R3            // b9ea1032
    	ADDW	R1, R2                // 1a21
    	ADDW	R1, R2, R3            // b9f81032
    	ADDW	$8192, R1             // a71a2000
    	ADDW	$8192, R1, R2         // ec21200000d8
    	ADDE	R1, R2                // b9880021
    	SUB	R3, R4                // b9090043
    	SUB	R3, R4, R5            // b9e93054
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Jul 30 19:29:15 UTC 2025
    - 22.9K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/arm64.s

    #include "../../../../../runtime/textflag.h"
    
    TEXT	foo(SB), DUPOK|NOSPLIT, $-8
    
    // arithmetic operations
    	ADDW	$1, R2, R3
    	ADDW	R1, R2, R3
    	ADDW	R1, ZR, R3
    	ADD	$1, R2, R3
    	ADD	R1, R2, R3
    	ADD	R1, ZR, R3
    	ADD	$1, R2, R3
    	ADDW	$1, R2
    	ADDW	R1, R2
    	ADD	$1, R2
    	ADD	R1, R2
    	ADD	R1>>11, R2
    	ADD	R1<<22, R2
    	ADD	R1->33, R2
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
    - 95.3K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/riscv64.s

    	SRLIW	$1, X5, X6				// 1bd31200
    	SRAIW	$1, X5, X6				// 1bd31240
    	ADDW	X5, X6, X7				// bb035300
    	SLLW	X5, X6, X7				// bb135300
    	SRLW	X5, X6, X7				// bb535300
    	SUBW	X5, X6, X7				// bb035340
    	SRAW	X5, X6, X7				// bb535340
    	ADDIW	$1, X6					// 1b031300
    	SLLIW	$1, X6					// 1b131300
    	SRLIW	$1, X6					// 1b531300
    	SRAIW	$1, X6					// 1b531340
    	ADDW	X5, X7					// bb835300
    	SLLW	X5, X7					// bb935300
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed May 21 14:19:19 UTC 2025
    - 49.1K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/arm64error.s

    	NEGSW	R7<<33, R5                                       // ERROR "shift amount out of range 0 to 31"
    	ADD	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	ADDW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	ADDS	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
    - 37.9K bytes
    - Viewed (0)
  5. lib/fips140/v1.0.0.zip

    or equal to the dst size. MOVD dst_len+40(FP), R4 CMP R0, R4 BGT crash MOVD R2, R4 MOVD R2, R6 MOVD R2, R8 MOVD R3, R5 MOVD R3, R7 MOVD R3, R9 ADDW $1, R5 ADDW $2, R7 ADDW $3, R9 incr: CMP R0, $64 BLT tail STMG R2, R9, (R1) ADDW $4, R3 ADDW $4, R5 ADDW $4, R7 ADDW $4, R9 MOVD $64(R1), R1 SUB $64, R0 BR incr tail: CMP R0, $0 BEQ crypt STMG R2, R3, (R1) ADDW $1, R3 MOVD $16(R1), R1 SUB $16, R0 BR tail crypt: STMG R2, R3, (R12) // update next counter value MOVD fn+0(FP), R0 // function code (encryption)...
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Jan 29 15:10:35 UTC 2025
    - 635K bytes
    - Viewed (0)
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