mlir::Operation *op = use.getOwner();
    if (llvm::isa<TF::TensorListGetItemOp>(op) ||
        llvm::isa<TF::TensorListLengthOp>(op) ||
        llvm::isa<TF::TensorListPushBackOp>(op) ||
        llvm::isa<TF::TensorListReserveOp>(op) ||
        llvm::isa<TF::TensorListSetItemOp>(op) ||
        llvm::isa<TF::TensorListStackOp>(op) ||
        llvm::isa<TF::TensorListResizeOp>(op)) {

func rewriteValuePPC64(v *Value) bool {
	switch v.Op {
	case OpAbs:
		v.Op = OpPPC64FABS
		return true
	case OpAdd16:
		v.Op = OpPPC64ADD
		return true
	case OpAdd32:
		v.Op = OpPPC64ADD
		return true
	case OpAdd32F:
		v.Op = OpPPC64FADDS
		return true
	case OpAdd64:
		v.Op = OpPPC64ADD
		return true
	case OpAdd64F:
		v.Op = OpPPC64FADD
		return true
	case OpAdd8:
		v.Op = OpPPC64ADD

    for (auto& op : graph->operators) {
      for (int idx = 0; idx < op->inputs.size(); idx++) {
        if (op->inputs[idx] < 0) {
          continue;
        }
        const auto& tensor = graph->tensors[op->inputs[idx]];
        auto* expected_tensor = FindMatchingExpectedTensor(
            *expected_graph, expected_model, model, *op, idx);
        if (!expected_tensor) {
          continue;

      rewriter.replaceOpWithNewOp<mhlo::GatherOp>(
          op, op.getType(), op.getParams(), op.getIndices(), dims_attr,
          GetI64ElementsAttr(slice_sizes, &rewriter));
    } else {
      rewriter.replaceOpWithNewOp<mhlo::DynamicGatherOp>(
          op, op.getType(), op.getParams(), op.getIndices(), slice_sizes_value,
          dims_attr);
    }
    return success();
  }
};

}

// Returns true if the op creates a TensorList.
bool IsTensorListInitOp(Operation* op) {
  return isa<TensorListReserveOp>(op) || isa<EmptyTensorListOp>(op) ||
         isa<TensorListFromTensorOp>(op);
}

// Returns the `element_shape` operand of the ops that create a TensorList.
Value GetElementShapeOperand(Operation* op) {
  if (auto empty_tl = dyn_cast<EmptyTensorListOp>(op))
    return empty_tl.getElementShape();

  // All TFLite ops has CPU interface, should be enough to check for cpu.
  return IsOpSupported(op, "CPU");
}

std::optional<std::string> GetDeviceName(mlir::Operation* op) {
  if (IsConst(op)) return std::nullopt;

  // The model may contain quant stats op which is unrelevant to the
  // execution.
  if (llvm::isa<mlir::func::ReturnOp, mlir::quantfork::StatisticsOp>(op))
    return std::nullopt;

func (b *Block) NewValue0(pos src.XPos, op Op, t *types.Type) *Value {
	v := b.Func.newValue(op, t, b, pos)
	v.AuxInt = 0
	v.Args = v.argstorage[:0]
	return v
}

// NewValue0I returns a new value in the block with no arguments and an auxint value.
func (b *Block) NewValue0I(pos src.XPos, op Op, t *types.Type, auxint int64) *Value {
	v := b.Func.newValue(op, t, b, pos)
	v.AuxInt = auxint
	v.Args = v.argstorage[:0]

  using OpRewritePattern::OpRewritePattern;
  LogicalResult matchAndRewrite(TF::OptionalFromValueOp op,
                                PatternRewriter& rewriter) const override {
    Value value = nullptr;
    for (auto v : op.getComponents()) {
      value = v;
    }
    if (!value) return failure();
    rewriter.replaceOpWithNewOp<TF::IdentityOp>(op, value.getType(), value);
    return success();
  }
};

        if (op->outputs()->Get(i) == tensor_idx) {
          const uint32_t op_code_idx = op->opcode_index();
          *op_code = GetBuiltinCode(model->operator_codes()->Get(op_code_idx));
          return true;
        }
      }
    }
    return false;
  }
};

// Returns true if everything between the two graphs
// are identical except for name field.

			}

			if hasIntrinsic {
				var op ssa.Op
				switch {
				case typ.Kind() == types.TFLOAT64 && n.Op() == ir.OMIN:
					op = ssa.OpMin64F
				case typ.Kind() == types.TFLOAT64 && n.Op() == ir.OMAX:
					op = ssa.OpMax64F
				case typ.Kind() == types.TFLOAT32 && n.Op() == ir.OMIN:
					op = ssa.OpMin32F
				case typ.Kind() == types.TFLOAT32 && n.Op() == ir.OMAX:
					op = ssa.OpMax32F
				}