usesScratch       bool      // this op requires scratch memory space
	hasSideEffects    bool      // for "reasons", not to be eliminated.  E.g., atomic store, #19182.
	zeroWidth         bool      // op never translates into any machine code. example: copy, which may sometimes translate to machine code, is not zero-width.

  %1 = "tf.Const"() {value = dense<[0, 0x4141, 3, 1]> : tensor<4xi32>} : () -> tensor<4xi32>
  %2 = "tf.Transpose"(%arg0, %0) : (tensor<1x4x4x8xf32>, tensor<4xi32>) -> tensor<1x8x4x4xf32>
  // expected-error @+1 {{'tf.Transpose' op perm[1]=16705 must be in range [-4, 4)}}
  %3 = "tf.Transpose"(%2, %1) : (tensor<1x8x4x4xf32>, tensor<4xi32>) -> tensor<1x4x4x8xf32>
  func.return %3 : tensor<1x4x4x8xf32>

---
name: TensorFlow Lite Op Request
about: Use this template for reporting Lite ops you are using or missing
labels: 'comp:lite'

---

**System information**
- OS Platform and Distribution (e.g., Linux Ubuntu 16.04):
- TensorFlow installed from (source or binary):
- TensorFlow version (or github SHA if from source):


**Provide the text output from tflite_convert**

```
# Copy and paste here
```

// RUN: tac-opt-all-backends -tfl-get-op-cost %s -split-input-file -verify-diagnostics | FileCheck %s

func.func @func_0_CPU(%arg0: tensor<256x32x32x3xf32>, %arg1: tensor<256x32x32x3xf32>) -> tensor<256x32x32x3xf32> attributes {tac.device = "CPU", tac.interface_name = "func_0"} {
  // CHECK: tac.cost = 7.864320e+05
  %0 = "tfl.add"(%arg0, %arg1) {fused_activation_function = "RELU", tac.device = "CPU"} : (tensor<256x32x32x3xf32>, tensor<256x32x32x3xf32>) -> tensor<256x32x32x3xf32>

# ==============================================================================

# Script for mlir-reduce to test input interestingness.
tf-opt $1 -tf-mark-ops-for-outside-compilation &> | grep "'tf.UnsupportedOp' op isn't compilable for TPU device"

if [ $? -eq 0 ]; then
  exit 1
else
  exit 0

	[2]Op{OpAMD64MOVWload, OpAMD64LEAQ1}:  OpAMD64MOVWloadidx1,
	[2]Op{OpAMD64MOVWload, OpAMD64LEAQ2}:  OpAMD64MOVWloadidx2,
	[2]Op{OpAMD64MOVLload, OpAMD64LEAQ1}:  OpAMD64MOVLloadidx1,
	[2]Op{OpAMD64MOVLload, OpAMD64LEAQ4}:  OpAMD64MOVLloadidx4,
	[2]Op{OpAMD64MOVLload, OpAMD64LEAQ8}:  OpAMD64MOVLloadidx8,
	[2]Op{OpAMD64MOVQload, OpAMD64LEAQ1}:  OpAMD64MOVQloadidx1,
	[2]Op{OpAMD64MOVQload, OpAMD64LEAQ8}:  OpAMD64MOVQloadidx8,

        op, op.getOutput().getType(), op.getScales(), op.getZeroPoints(),
        /*expressed_type=*/rewriter.getF32Type(), op.getQuantizationMinVal(),
        op.getQuantizationMaxVal(), op.getQuantizationAxis(), rewriter);
    if (failed(output_type)) {
      return failure();
    }

    auto result = rewriter.create<mhlo::UniformQuantizeOp>(
        op->getLoc(), *output_type, op.getInput());

	op := &PortAllocationOperation{}
	op.pa = pa
	op.allocated = []int{}
	op.releaseDeferred = []int{}
	op.shouldRollback = true
	op.dryRun = dryRun
	return op
}

// Will rollback unless marked as shouldRollback = false by a Commit().  Call from a defer block
func (op *PortAllocationOperation) Finish() {
	if op.shouldRollback {
		op.Rollback()
	}
}

    << '(' << op.getArgs() << ')';

  fallback_common::PrintExecuteOpCommon(p, op);
  fallback_common::PrintExecuteOpFuncAttribute(p, op);
  if (!op.getResults().empty()) p << " : " << op.getResults().size();
}

void ExecuteOpSeqWithAllocator::print(OpAsmPrinter &p) {
  ExecuteOpSeqWithAllocator op = *this;
  p << "(" << op.getInOpChain() << ", " << op.getAllocator() << ") key("

  TF_RETURN_IF_ERROR(
      GetNodeAttr(op.node()->attrs(), "is_training", &is_training));

  std::vector<Output> reserve_spaces;
  reserve_spaces.push_back(op.output(3));
  reserve_spaces.push_back(op.output(4));
  if (op.num_outputs() > 5) {
    reserve_spaces.push_back(op.output(5));
  }

  if (is_training) {