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Results 1 - 7 of 7 for 16xi32 (0.1 sec)

  1. tensorflow/compiler/mlir/lite/tests/legalize-tf.mlir

    // CHECK:  return
    }
    
    func.func @addV2(%arg0: tensor<1xi32>, %arg1: tensor<1xi32>) -> tensor<1xi32> {
      %0 = "tf.AddV2"(%arg0, %arg1) : (tensor<1xi32>, tensor<1xi32>) -> tensor<1xi32>
      func.return %0 : tensor<1xi32>
    
    // CHECK-LABEL: addV2
    // CHECK:  tfl.add %arg0, %arg1 {fused_activation_function = "NONE"} : tensor<1xi32>
    }
    
    func.func @addV2I16(%arg0: tensor<1xi16>, %arg1: tensor<1xi16>) -> tensor<1xi16> {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Jun 05 01:54:33 UTC 2024
    - 153.4K bytes
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  2. tensorflow/compiler/mlir/lite/tests/ops.mlir

    // -----
    
    func.func @testFusedActivationFunction(%arg0: tensor<4xi32>, %arg1: tensor<4xi32>) -> (tensor<4xi32>, tensor<4xi32>, tensor<4xi32>, tensor<4xi32>, tensor<4xi32>, tensor<4xi32>) {
      // CHECK: "NONE"
      %0 = tfl.add %arg0, %arg1 {fused_activation_function = "NONE"} : tensor<4xi32>
      // CHECK: "RELU"
      %1 = tfl.add %arg0, %arg1 {fused_activation_function = "RELU"} : tensor<4xi32>
      // CHECK: "RELU_N1_TO_1"
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Jun 06 19:09:08 UTC 2024
    - 189.2K bytes
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  3. tensorflow/compiler/mlir/tfrt/tests/ifrt/sink_variable_as_named_array.mlir

        %cst = "tf.Const"() <{value = dense<[1]> : tensor<1xi32>}> : () -> tensor<1xi32>
        %0 = "tf.VarHandleOp"() <{container = "", shared_name = "Variable"}> : () -> tensor<!tf_type.resource<tensor<2x3xbf16>>>
        %1 = "tf.ResourceGather"(%0, %cst) <{batch_dims = 0 : i64, validate_indices = true}> : (tensor<!tf_type.resource<tensor<2x3xbf16>>>, tensor<1xi32>) -> tensor<1x3xbf16>
        return %1: tensor<1x3xbf16>
      }
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Jun 06 15:33:17 UTC 2024
    - 5.3K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tensorflow/transforms/tf_passes.td

        ```mlir
          %2 = "tf.A"(%arg0) : (tensor<?xi32>) -> tensor<?xi32>
          %3 = "tf.B"(%2) {device = "tpu0"} : (tensor<?xi32>) -> tensor<?xi32>
          %4 = "tf.C"(%2, %3) {device = "tpu0"} : (tensor<?xi32>, tensor<?xi32>) -> tensor<?xi32>
          %5 = "tf.D"(%4) : (tensor<?xi32>) -> tensor<?xi32>
        ```
    
        After the pass, we will have:
    
        ```mlir
          %0 = "tf.A"(%arg0) : (tensor<?xi32>) -> tensor<?xi32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Jun 12 21:18:05 UTC 2024
    - 99.6K bytes
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  5. tensorflow/compiler/mlir/tensorflow/transforms/shape_inference.cc

      // The first Operand is assumed to be a TensorType around a variant with a
      // single subtype (e.g. tensor<!tf_type.variant<tensor<2xi32>>>). We will
      // copy this type to the first result, and copy the singular variant subtype
      // to the second result (tensor<2xi32>).
      DCOMMENT_OP(op, "Inferring shape for TensorListPopBackOp.");
    
      auto src_list_handle_t =
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sat Jun 08 07:28:49 UTC 2024
    - 134.1K bytes
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  6. tensorflow/compiler/mlir/tensorflow/ir/tf_generated_ops.td

    from tensorflow.compiler.mlir.tensorflow.gen_mlir_passthrough_op import mlir_passthrough_op
    
    mlir_module = '''python
    func @main(%arg0 : tensor<10xf32>, %arg1 : tensor<10xf32>) -> tensor<10x10xf32> {
       %add = "magic.op"(%arg0, %arg1) : (tensor<10xf32>, tensor<10xf32>) -> tensor<10x10xf32>
       return %ret : tensor<10x10xf32>
    }
    '''
    
    @tf.function
    def foo(x, y):
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 11 23:24:08 UTC 2024
    - 793K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/rewritePPC64.go

    		if z.Op != OpPPC64MOVHZreg {
    			break
    		}
    		x := z.Args[0]
    		if !(z.Uses == 1 && c < 16) {
    			break
    		}
    		v.reset(OpPPC64CLRLSLWI)
    		v.AuxInt = int32ToAuxInt(newPPC64ShiftAuxInt(c, 16, 31, 32))
    		v.AddArg(x)
    		return true
    	}
    	// match: (SLWconst [c] z:(ANDconst [d] x))
    	// cond: z.Uses == 1 && isPPC64ValidShiftMask(d) && c<=(32-getPPC64ShiftMaskLength(d))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 360.2K bytes
    - Viewed (0)
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