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Results 1 - 10 of 24 for rreg (4.82 sec)
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src/cmd/asm/internal/asm/testdata/mips64.s
// LFADD freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } ADDD F1, F2 // LFADD freg ',' freg ',' freg // { // outcode(int($1), &$2, int($4.Reg), &$6); // } ADDD F1, F2, F3 // LFCMP freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } CMPEQD F1, F2 // // WORD // WORD $1 // 00000001 NOOP // 00000000 SYNC // 0000000f //
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 12.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// } ADD $4, R1 // LMUL rreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MUL R1, R2 // LSHW rreg ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } SLL R1, R2, R3 // LSHW rreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SLL R1, R2 // LSHW imm ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // }
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 6.7K bytes - Viewed (0) -
src/cmd/asm/internal/arch/ppc64.go
case "CR": if 0 <= n && n <= 7 { return ppc64.REG_CR0 + n, true } case "A": if 0 <= n && n <= 8 { return ppc64.REG_A0 + n, true } case "VS": if 0 <= n && n <= 63 { return ppc64.REG_VS0 + n, true } case "V": if 0 <= n && n <= 31 { return ppc64.REG_V0 + n, true } case "F": if 0 <= n && n <= 31 { return ppc64.REG_F0 + n, true } case "R": if 0 <= n && n <= 31 {
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Sep 07 20:53:33 GMT 2022 - 2.2K bytes - Viewed (0) -
src/cmd/asm/internal/arch/s390x.go
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Thu Oct 17 14:55:25 GMT 2019 - 1.2K bytes - Viewed (0) -
api/go1.13.txt
pkg syscall (netbsd-arm64-cgo), const DT_FIFO ideal-int pkg syscall (netbsd-arm64-cgo), const DT_LNK = 10 pkg syscall (netbsd-arm64-cgo), const DT_LNK ideal-int pkg syscall (netbsd-arm64-cgo), const DT_REG = 8 pkg syscall (netbsd-arm64-cgo), const DT_REG ideal-int pkg syscall (netbsd-arm64-cgo), const DT_SOCK = 12 pkg syscall (netbsd-arm64-cgo), const DT_SOCK ideal-int pkg syscall (netbsd-arm64-cgo), const DT_UNKNOWN = 0
Plain Text - Registered: Tue May 07 11:14:38 GMT 2024 - Last Modified: Thu Aug 08 18:44:16 GMT 2019 - 452.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
// MULL r1,r2,(hi,lo) // // LTYPEM cond reg ',' reg ',' regreg // { // outcode($1, $2, &$3, int32($5.Reg), &$7); // } MULL R1, R2, (R3,R4) // // MULA r1,r2,r3,r4: (r1*r2+r3) & 0xffffffff . r4 // MULAW{T,B} r1,r2,r3,r4 // // LTYPEN cond reg ',' reg ',' reg ',' spreg // { // $7.Type = obj.TYPE_REGREG2; // $7.Offset = int64($9); // outcode($1, $2, &$3, int32($5.Reg), &$7); // } MULAWT R1, R2, R3, R4
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 15 20:51:01 GMT 2023 - 69K bytes - Viewed (0) -
src/cmd/asm/internal/arch/loong64.go
switch name { case "F": if 0 <= n && n <= 31 { return loong64.REG_F0 + n, true } case "FCSR": if 0 <= n && n <= 31 { return loong64.REG_FCSR0 + n, true } case "FCC": if 0 <= n && n <= 31 { return loong64.REG_FCC0 + n, true } case "R": if 0 <= n && n <= 31 { return loong64.REG_R0 + n, true } } return 0, false
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Mon Feb 06 13:49:53 GMT 2023 - 2.1K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm.go
return true } return false } // IsARMBFX reports whether the op (as defined by an arm.A* constant) is one the // BFX-like instructions which are in the form of "op $width, $LSB, (Reg,) Reg". func IsARMBFX(op obj.As) bool { switch op { case arm.ABFX, arm.ABFXU, arm.ABFC, arm.ABFI: return true } return false }
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Nov 18 17:59:44 GMT 2022 - 6.1K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arch.go
register["S0"] = riscv.REG_S0 register["S1"] = riscv.REG_S1 register["A0"] = riscv.REG_A0 register["A1"] = riscv.REG_A1 register["A2"] = riscv.REG_A2 register["A3"] = riscv.REG_A3 register["A4"] = riscv.REG_A4 register["A5"] = riscv.REG_A5 register["A6"] = riscv.REG_A6 register["A7"] = riscv.REG_A7 register["S2"] = riscv.REG_S2 register["S3"] = riscv.REG_S3 register["S4"] = riscv.REG_S4
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Mar 21 06:51:28 GMT 2023 - 21.3K bytes - Viewed (0) -
api/go1.txt
pkg syscall (windows-386), const REG_MULTI_SZ ideal-int pkg syscall (windows-386), const REG_NONE ideal-int pkg syscall (windows-386), const REG_QWORD ideal-int pkg syscall (windows-386), const REG_QWORD_LITTLE_ENDIAN ideal-int pkg syscall (windows-386), const REG_RESOURCE_LIST ideal-int pkg syscall (windows-386), const REG_RESOURCE_REQUIREMENTS_LIST ideal-int pkg syscall (windows-386), const REG_SZ ideal-int
Plain Text - Registered: Tue May 07 11:14:38 GMT 2024 - Last Modified: Wed Aug 14 18:58:28 GMT 2013 - 1.7M bytes - Viewed (2)