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src/cmd/asm/internal/asm/testdata/riscv64error.s
SD X5, 4294967296(X6) // ERROR "constant 4294967296 too large" SRLI $1, X5, F1 // ERROR "expected integer register in rd position but got non-integer register F1" SRLI $1, F1, X5 // ERROR "expected integer register in rs1 position but got non-integer register F1" FNES F1, (X5) // ERROR "needs an integer register output"
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Sun Apr 07 03:32:27 GMT 2024 - 2.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
//TODO: this compiles to add r5,r6,r0. It should be addi r5,r6,0. // this is OK since r0 == $0, but the latter is preferred. ADD $0, R6, R5 // 7ca60214 //TODO: the assembler rewrites these into ADDIS $19, R5, Rx and ADD $-10617, Rx, Rx, but the test only sees the first ADDIS ADD $1234567, R5 // 3ca50013 or 0600001238a5d687
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Apr 24 15:53:25 GMT 2024 - 49K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
MOVQ DR7, SI // 0f21fe // Test other movtab entries. PUSHQ GS // 0fa8 PUSHQ FS // 0fa0 POPQ FS // 0fa1 POPQ GS // 0fa9 // All instructions below semantically have unsigned operands, // but previous assembler permitted negative arguments. // This behavior is preserved for compatibility reasons. VPSHUFD $-79, X7, X7 // c5f970ffb1 RORXL $-1, (AX), DX // c4e37bf010ff
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Apr 11 18:32:50 GMT 2023 - 57.6K bytes - Viewed (0)