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  1. src/cmd/asm/internal/asm/testdata/riscv64error.s

    // Copyright 2021 The Go Authors. All rights reserved.
    // Use of this source code is governed by a BSD-style
    // license that can be found in the LICENSE file.
    
    TEXT errors(SB),$0
    	MOV	$errors(SB), (X5)		// ERROR "address load must target register"
    	MOV	$8(SP), (X5)			// ERROR "address load must target register"
    	MOVB	$8(SP), X5			// ERROR "unsupported address load"
    	MOVH	$8(SP), X5			// ERROR "unsupported address load"
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Sun Apr 07 03:32:27 GMT 2024
    - 2.8K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/arm.s

    // Copyright 2015 The Go Authors. All rights reserved.
    // Use of this source code is governed by a BSD-style
    // license that can be found in the LICENSE file.
    
    // This input was created by taking the instruction productions in
    // the old assembler's (5a's) grammar and hand-writing complete
    // instructions for each rule, to guarantee we cover the same space.
    
    #include "../../../../../runtime/textflag.h"
    
    TEXT	foo(SB), DUPOK|NOSPLIT, $0
    
    // ADD
    //
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Dec 15 20:51:01 GMT 2023
    - 69K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/riscv64.s

    // Copyright 2019 The Go Authors. All rights reserved.
    // Use of this source code is governed by a BSD-style
    // license that can be found in the LICENSE file.
    
    #include "../../../../../runtime/textflag.h"
    
    TEXT asmtest(SB),DUPOK|NOSPLIT,$0
    start:
    	// Unprivileged ISA
    
    	// 2.4: Integer Computational Instructions
    
    	ADDI	$2047, X5				// 9382f27f
    	ADDI	$-2048, X5				// 93820280
    	ADDI	$2048, X5				// 9382024093820240
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Mar 22 04:42:21 GMT 2024
    - 16.7K bytes
    - Viewed (1)
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