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src/cmd/asm/internal/asm/testdata/ppc64.s
// This only captures the MOVD. Should the SLD be appended to the encoding by the test? // Hex constant 0x20004000000 MOVD $2199090364416, R5 // 60058001 // Hex constant 0xFFFFFE0004000000 MOVD $-2198956146688, R5 // 38a08001 // TODO: On GOPPC64={power8,power9}, this is preprocessed into MOVD $-1, R5; RLDC R5, $33, $63, R5. // This only captures the MOVD. Should the RLDC be appended to the encoding by the test?
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Apr 24 15:53:25 GMT 2024 - 49K bytes - Viewed (0) -
.github/ISSUE_TEMPLATE/11-language-change.yml
attributes: label: "Orthogonality: How does this change interact or overlap with existing features?" description: "Is the goal of this change a performance improvement? If so, what quantifiable improvement should we expect? How would we measure it?" validations: required: false - type: textarea id: learning-curve attributes:
Others - Registered: Tue May 07 11:14:38 GMT 2024 - Last Modified: Wed Nov 22 20:49:24 GMT 2023 - 4.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
SLL R5, R6, R7 // 1675a0e1 SLL.S R5, R6, R7 // 1675b0e1 SLL R5, R7 // 1775a0e1 SLL.S R5, R7 // 1775b0e1 // Ops with zero shifts should encode as left shifts ADD R0<<0, R1, R2 // 002081e0 ADD R0>>0, R1, R2 // 002081e0 ADD R0->0, R1, R2 // 002081e0 ADD R0@>0, R1, R2 // 002081e0 MOVW R0<<0(R1), R2 // 002091e7
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 15 20:51:01 GMT 2023 - 69K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
lable1: BFPT 1(PC) // 00050048 BFPT lable1 // BFPT 2 //1ffdff4b lable2: BFPF 1(PC) // 00040048 BFPF lable2 // BFPF 4 // 1ffcff4b // relocation in play so the assembled offset should be 0 JMP foo(SB) // 00000050 JMP (R4) // 8000004c JMP 1(PC) // 00040050 MOVW $65536, R4 // 04020014 MOVW $4096, R4 // 24000014 MOVV $65536, R4 // 04020014 MOVV $4096, R4 // 24000014
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Mar 31 02:56:19 GMT 2023 - 6.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64error.s
VPGATHERDQ X2, 664(X2*8), X7 // ERROR "mask, index, and destination registers should be distinct" VPGATHERDQ X2, 664(X7*8), X2 // ERROR "mask, index, and destination registers should be distinct" VPGATHERDQ X7, 664(X2*8), X2 // ERROR "mask, index, and destination registers should be distinct" // Non-X0 for Yxr0 should produce an error BLENDVPD X1, (BX), X2 // ERROR "invalid instruction"
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Jun 14 00:03:57 GMT 2023 - 8.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64.s
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Mar 22 18:50:59 GMT 2023 - 434 bytes - Viewed (0)