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Results 1 - 5 of 5 for rotw (0.06 sec)
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src/cmd/asm/internal/asm/testdata/amd64enc.s
//TODO: RETFQ $0xf123 // ca23f1 ROLW $1, (BX) // 66d103 ROLW $1, (R11) // 6641d103 ROLW $1, DX // 66d1c2 ROLW $1, R11 // 6641d1c3 ROLW CL, (BX) // 66d303 ROLW CL, (R11) // 6641d303 ROLW CL, DX // 66d3c2
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Fri Oct 08 21:38:44 UTC 2021 - 581.9K bytes - Viewed (1) -
src/main/webapp/css/admin/bootstrap.min.css.map
ve-4by3::before {\n padding-top: 75%;\n}\n\n.embed-responsive-1by1::before {\n padding-top: 100%;\n}\n\n.flex-row {\n -ms-flex-direction: row !important;\n flex-direction: row !important;\n}\n\n.flex-column {\n -ms-flex-direction: column !important;\n flex-direction: column !important;\n}\n\n.flex-row-reverse {\n -ms-flex-direction: row-reverse !important;\n flex-direction: row-reverse !important;\n}\n\n.flex-column-reverse {\n -ms-flex-direction: column-reverse !important;\n flex-direction:...
Registered: Thu Sep 04 12:52:25 UTC 2025 - Last Modified: Sat Oct 26 01:49:09 UTC 2024 - 639.3K bytes - Viewed (1) -
src/main/webapp/css/bootstrap.min.css.map
-3 {\n gap: 1rem !important;\n}\n\n.gap-4 {\n gap: 1.5rem !important;\n}\n\n.gap-5 {\n gap: 3rem !important;\n}\n\n.row-gap-0 {\n row-gap: 0 !important;\n}\n\n.row-gap-1 {\n row-gap: 0.25rem !important;\n}\n\n.row-gap-2 {\n row-gap: 0.5rem !important;\n}\n\n.row-gap-3 {\n row-gap: 1rem !important;\n}\n\n.row-gap-4 {\n row-gap: 1.5rem !important;\n}\n\n.row-gap-5 {\n row-gap: 3rem !important;\n}\n\n.column-gap-0 {\n -moz-column-gap: 0 !important;\n column-gap: 0 !important;\n}\n\n.column-gap-1...
Registered: Thu Sep 04 12:52:25 UTC 2025 - Last Modified: Sun Jan 12 06:14:02 UTC 2025 - 575.5K bytes - Viewed (0) -
lib/fips140/v1.0.0.zip
SIGMA0(Wt-15) + Wt-16; for 16 <= t <= 63 // SIGMA0(x) = ROTR(7,x) XOR ROTR(18,x) XOR SHR(3,x) // SIGMA1(x) = ROTR(17,x) XOR ROTR(19,x) XOR SHR(10,x) #define MSGSCHEDULE1(index) \ MOVWU (((index-2)&0xf)*4)(X19), X5; \ MOVWU (((index-15)&0xf)*4)(X19), X6; \ MOVWU (((index-7)&0xf)*4)(X19), X9; \ MOVWU (((index-16)&0xf)*4)(X19), X21; \ RORW $17, X5, X7; \ RORW $19, X5, X8; \ SRL $10, X5; \ XOR X7, X5; \ XOR X8, X5; \ ADD X9, X5; \ RORW $7, X6, X7; \ RORW $18, X6, X8; \ SRL $3, X6; \ XOR X7, X6; \ XOR X8,...
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Jan 29 15:10:35 UTC 2025 - 635K bytes - Viewed (0) -
RELEASE.md
* TPUs can now be re-initialized multiple times, using `tf.tpu.experimental.initialize_tpu_system`. * Add `RaggedTensor.merge_dims()`. * Added new `uniform_row_length` row-partitioning tensor to `RaggedTensor`. * Add `shape` arg to `RaggedTensor.to_tensor`; Improve speed of `RaggedTensor.to_tensor`.
Registered: Tue Sep 09 12:39:10 UTC 2025 - Last Modified: Mon Aug 18 20:54:38 UTC 2025 - 740K bytes - Viewed (1)