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Results 1 - 6 of 6 for rotw (0.46 seconds)

  1. lib/fips140/v1.26.0.zip

    SIGMA0(Wt-15) + Wt-16; for 16 <= t <= 63 // SIGMA0(x) = ROTR(7,x) XOR ROTR(18,x) XOR SHR(3,x) // SIGMA1(x) = ROTR(17,x) XOR ROTR(19,x) XOR SHR(10,x) #define MSGSCHEDULE1(index) \ MOVWU (((index-2)&0xf)*4)(X19), X5; \ MOVWU (((index-15)&0xf)*4)(X19), X6; \ MOVWU (((index-7)&0xf)*4)(X19), X9; \ MOVWU (((index-16)&0xf)*4)(X19), X21; \ RORW $17, X5, X7; \ RORW $19, X5, X8; \ SRL $10, X5; \ XOR X7, X5; \ XOR X8, X5; \ ADD X9, X5; \ RORW $7, X6, X7; \ RORW $18, X6, X8; \ SRL $3, X6; \ XOR X7, X6; \ XOR X8,...
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Thu Jan 08 17:58:32 GMT 2026
    - 660.3K bytes
    - Click Count (0)
  2. lib/fips140/v1.0.0-c2097c7c.zip

    SIGMA0(Wt-15) + Wt-16; for 16 <= t <= 63 // SIGMA0(x) = ROTR(7,x) XOR ROTR(18,x) XOR SHR(3,x) // SIGMA1(x) = ROTR(17,x) XOR ROTR(19,x) XOR SHR(10,x) #define MSGSCHEDULE1(index) \ MOVWU (((index-2)&0xf)*4)(X19), X5; \ MOVWU (((index-15)&0xf)*4)(X19), X6; \ MOVWU (((index-7)&0xf)*4)(X19), X9; \ MOVWU (((index-16)&0xf)*4)(X19), X21; \ RORW $17, X5, X7; \ RORW $19, X5, X8; \ SRL $10, X5; \ XOR X7, X5; \ XOR X8, X5; \ ADD X9, X5; \ RORW $7, X6, X7; \ RORW $18, X6, X8; \ SRL $3, X6; \ XOR X7, X6; \ XOR X8,...
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Thu Sep 25 19:53:19 GMT 2025
    - 642.7K bytes
    - Click Count (0)
  3. src/main/webapp/css/admin/bootstrap.min.css.map

    ve-4by3::before {\n  padding-top: 75%;\n}\n\n.embed-responsive-1by1::before {\n  padding-top: 100%;\n}\n\n.flex-row {\n  -ms-flex-direction: row !important;\n  flex-direction: row !important;\n}\n\n.flex-column {\n  -ms-flex-direction: column !important;\n  flex-direction: column !important;\n}\n\n.flex-row-reverse {\n  -ms-flex-direction: row-reverse !important;\n  flex-direction: row-reverse !important;\n}\n\n.flex-column-reverse {\n  -ms-flex-direction: column-reverse !important;\n  flex-direction:...
    Created: Tue Mar 31 13:07:34 GMT 2026
    - Last Modified: Sat Oct 26 01:49:09 GMT 2024
    - 639.3K bytes
    - Click Count (1)
  4. src/cmd/asm/internal/asm/testdata/amd64enc.s

    	//TODO: RETFQ $0xf123                   // ca23f1
    	ROLW $1, (BX)                           // 66d103
    	ROLW $1, (R11)                          // 6641d103
    	ROLW $1, DX                             // 66d1c2
    	ROLW $1, R11                            // 6641d1c3
    	ROLW CL, (BX)                           // 66d303
    	ROLW CL, (R11)                          // 6641d303
    	ROLW CL, DX                             // 66d3c2
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Fri Oct 08 21:38:44 GMT 2021
    - 581.9K bytes
    - Click Count (1)
  5. src/main/webapp/css/bootstrap.min.css.map

    -3 {\n  gap: 1rem !important;\n}\n\n.gap-4 {\n  gap: 1.5rem !important;\n}\n\n.gap-5 {\n  gap: 3rem !important;\n}\n\n.row-gap-0 {\n  row-gap: 0 !important;\n}\n\n.row-gap-1 {\n  row-gap: 0.25rem !important;\n}\n\n.row-gap-2 {\n  row-gap: 0.5rem !important;\n}\n\n.row-gap-3 {\n  row-gap: 1rem !important;\n}\n\n.row-gap-4 {\n  row-gap: 1.5rem !important;\n}\n\n.row-gap-5 {\n  row-gap: 3rem !important;\n}\n\n.column-gap-0 {\n  -moz-column-gap: 0 !important;\n  column-gap: 0 !important;\n}\n\n.column-gap-1...
    Created: Tue Mar 31 13:07:34 GMT 2026
    - Last Modified: Sun Jan 12 06:14:02 GMT 2025
    - 575.5K bytes
    - Click Count (0)
  6. RELEASE.md

        *   TPUs can now be re-initialized multiple times, using
            `tf.tpu.experimental.initialize_tpu_system`.
        *   Add `RaggedTensor.merge_dims()`.
        *   Added new `uniform_row_length` row-partitioning tensor to
            `RaggedTensor`.
        *   Add `shape` arg to `RaggedTensor.to_tensor`; Improve speed of
            `RaggedTensor.to_tensor`.
    Created: Tue Apr 07 12:39:13 GMT 2026
    - Last Modified: Mon Mar 30 18:31:38 GMT 2026
    - 746.5K bytes
    - Click Count (3)
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