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Results 1 - 4 of 4 for divr (0.06 sec)
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src/cmd/asm/internal/asm/testdata/amd64enc.s
DIVQ (BX) // 48f733 DIVQ (R11) // 49f733 DIVQ DX // 48f7f2 DIVQ R11 // 49f7f3 DIVB (BX) // f633 DIVB (R11) // 41f633 DIVB DL // f6f2 DIVB R11 // 41f6f3
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Oct 08 21:38:44 UTC 2021 - 581.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteAMD64.go
return true } } func rewriteValueAMD64_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 712.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritegeneric.go
} v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log8(c)) v.AddArg2(n, v0) return true } // match: (Div8 <t> n (Const8 [c])) // cond: c < 0 && c != -1<<7 // result: (Neg8 (Div8 <t> n (Const8 <t> [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 22 18:24:47 UTC 2024 - 812.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM64.go
b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (DIVW (SignExt8to32 x) (SignExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 608.6K bytes - Viewed (0)