BCL $20,CR0LT,$1,LR             // 4e800821
	BCL $20,CR0LT,$0,LR             // 4e800021
	BCL $20,CR0LT,LR                // 4e800021
	BCL $20,CR0GT,LR                // 4e810021
	BCL 20,CR0LT,LR                 // BCL $20,CR0LT,LR // 4e800021
	BCL 20,undefined_symbol,LR      // BCL $20,CR0LT,LR // 4e800021
	BCL 20,undefined_symbol+1,LR    // BCL $20,CR0GT,LR // 4e810021

	OP_TOCSAVE       = 0xf8410018 // std r2,24(r1)
	OP_NOP           = 0x60000000 // nop
	OP_BL            = 0x48000001 // bl 0
	OP_BCTR          = 0x4e800420 // bctr
	OP_BCTRL         = 0x4e800421 // bctrl
	OP_BCL           = 0x40000001 // bcl
	OP_ADDI          = 0x38000000 // addi
	OP_ADDIS         = 0x3c000000 // addis
	OP_LD            = 0xe8000000 // ld
	OP_PLA_PFX       = 0x06100000 // pla (prefix instruction word)

			AREM, AREMU, AREMW, AREMUW,
			AADDUW, ASH1ADD, ASH1ADDUW, ASH2ADD, ASH2ADDUW, ASH3ADD, ASH3ADDUW, ASLLIUW,
			AANDN, AORN, AXNOR, AMAX, AMAXU, AMIN, AMINU, AROL, AROLW, AROR, ARORW, ARORI, ARORIW,
			ABCLR, ABCLRI, ABEXT, ABEXTI, ABINV, ABINVI, ABSET, ABSETI:
			p.Reg = p.To.Reg
		}
	}

	// Rewrite instructions with constant operands to refer to the immediate
	// form of the instruction.

		{name: "FlagEQ"}, // CC=0 (equal)
		{name: "FlagLT"}, // CC=1 (less than)
		{name: "FlagGT"}, // CC=2 (greater than)
		{name: "FlagOV"}, // CC=3 (overflow)

		// Fast-BCR-serialization to ensure store-load ordering.
		{name: "SYNC", argLength: 1, reg: sync, asm: "SYNC", typ: "Mem"},

		// Atomic loads. These are just normal loads but return <value,memory> tuples

		}

		pp := s.Call(v)

		// Convert the call into a blrl with hint this is not a subroutine return.
		// The full bclrl opcode must be specified when passing a hint.
		pp.As = ppc64.ABCL
		pp.From.Type = obj.TYPE_CONST
		pp.From.Offset = ppc64.BO_ALWAYS
		pp.Reg = ppc64.REG_CR0LT // The preferred value if BI is ignored.

(RoundToEven x) => (FIDBR [4] x)
(Round       x) => (FIDBR [1] x)
(FMA     x y z) => (FMADD z x y)

(Sqrt32    ...) => (FSQRTS ...)

// Atomic loads and stores.
// The SYNC instruction (fast-BCR-serialization) prevents store-load
// reordering. Other sequences of memory operations (load-load,
// store-store and load-store) are already guaranteed not to be reordered.

�b��hUb�0���]T(�9��Q��e�}�!�A��+���	����t��o<�K�S#ro|��hT�Ί��Td ����W���3�؁Nt2��ܳ�!2���z�T;	Ծ��s�&V<�R�O��rq��5����/x�!�P=�H�N޽�8�;~��j/?�ܾ+&DM����l����B� �)C5��BcR��Ų@�����L��z���xW�M1U���~߬�xl4��\����4R�E�NX�\��ͫ��`lc��|.F]xP]�`G�t\�,Ż�������[����lp�+^�9ԃ)[��_�
�{�LH���~�rG�^�u���h��׵r\�Vp��������)��=���9-���4��3_
��W0/!
�ᘮ��uG���W�)e[�y=��J�$-�6dw�:��