MSR	R4, CNTP_CVAL_EL0                  // 44e21bd5
	MRS	CNTP_TVAL_EL0, R27                 // 1be23bd5
	MSR	R17, CNTP_TVAL_EL0                 // 11e21bd5
	MRS	CNTV_CTL_EL0, R27                  // 3be33bd5
	MSR	R2, CNTV_CTL_EL0                   // 22e31bd5
	MRS	CNTV_CVAL_EL0, R16                 // 50e33bd5
	MSR	R27, CNTV_CVAL_EL0                 // 5be31bd5
	MRS	CNTV_TVAL_EL0, R12                 // 0ce33bd5

//    Upper bytes are junk.
//  - *const instructions may use a constant larger than the instruction can encode.
//    In this case the assembler expands to multiple instructions and uses tmp
//    register (R27).
//  - All 32-bit Ops will zero the upper 32 bits of the destination register.

// Suffixes encode the bit width of various instructions.
// D (double word) = 64 bit
// W (word)        = 32 bit
// H (half word)   = 16 bit