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Results 1 - 3 of 3 for srw (0.02 sec)
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src/cmd/compile/internal/ssa/rewrite.go
// or return 0 if they cannot be combined. func mergePPC64SldiSrw(sld, srw int64) int64 { if sld > srw || srw >= 32 { return 0 } mask_r := uint32(0xFFFFFFFF) >> uint(srw) mask_l := uint32(0xFFFFFFFF) >> uint(sld) mask := (mask_r & mask_l) << uint(sld) return encodePPC64RotateMask((32-srw+sld)&31, int64(mask), 32) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 64.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
SLWCC R3, R4 // 7c841831 SLD $16, R3, R4 // 786483e4 SLD R3, R4, R5 // 7c851836 SLDCC R3, R4 // 7c841837 SRW $8, R3, R4 // 5464c23e SRW R3, R4, R5 // 7c851c30 SRWCC R3, R4 // 7c841c31 SRAW $8, R3, R4 // 7c644670 SRAW R3, R4, R5 // 7c851e30
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(Lsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y) (Lsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y) (Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD x y) (Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRW x y) (Rsh16Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD (MOVHZreg x) y) (Rsh8Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD (MOVBZreg x) y) (Rsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD x y)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0)