- Sort Score
- Result 10 results
- Languages All
Results 1 - 9 of 9 for auxint (0.51 sec)
-
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
{name: "RORWconst", argLength: 1, reg: gp11, asm: "RORW", aux: "Int64"}, // uint32(arg0) right rotate by auxInt bits, auxInt should be in the range 0 to 31. {name: "EXTRconst", argLength: 2, reg: gp21, asm: "EXTR", aux: "Int64"}, // extract 64 bits from arg0:arg1 starting at lsb auxInt, auxInt should be in the range 0 to 63.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
src/cmd/compile/internal/ppc64/ssa.go
case ssa.OpPPC64ISEL, ssa.OpPPC64ISELZ: // ISEL AuxInt ? arg0 : arg1 // ISELZ is a special case of ISEL where arg1 is implicitly $0. // // AuxInt value indicates conditions 0=LT 1=GT 2=EQ 3=SO 4=GE 5=LE 6=NE 7=NSO. // ISEL accepts a CR bit argument, not a condition as expressed by AuxInt. // Convert the condition to a CR bit argument by the following conversion: // // AuxInt&3 ? arg0 : arg1 for conditions LT, GT, EQ, SO
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 55.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewrite.go
func DecodePPC64RotateMask(sauxint int64) (rotate, mb, me int64, mask uint64) { auxint := uint64(sauxint) rotate = int64((auxint >> 16) & 0xFF) mb = int64((auxint >> 8) & 0xFF) me = int64((auxint >> 0) & 0xFF) nbits := int64((auxint >> 24) & 0xFF) mask = ((1 << uint(nbits-mb)) - 1) ^ ((1 << uint(nbits-me)) - 1) if mb > me { mask = ^mask } if nbits == 32 {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 64.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(SRWconst (ANDconst [m] x) [s]) && mergePPC64RShiftMask(m>>uint(s),s,32) == 0 => (MOVDconst [0]) (SRWconst (ANDconst [m] x) [s]) && mergePPC64AndSrwi(m>>uint(s),s) != 0 => (RLWINM [mergePPC64AndSrwi(m>>uint(s),s)] x) (SRWconst (AND (MOVDconst [m]) x) [s]) && mergePPC64RShiftMask(m>>uint(s),s,32) == 0 => (MOVDconst [0]) (SRWconst (AND (MOVDconst [m]) x) [s]) && mergePPC64AndSrwi(m>>uint(s),s) != 0 => (RLWINM [mergePPC64AndSrwi(m>>uint(s),s)] x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/debug.go
} synthesizeOpIntFloatArg := func(n *ir.Name, t *types.Type, reg abi.RegIndex, sl LocalSlot) *Value { aux := &AuxNameOffset{n, sl.Off} op, auxInt := ArgOpAndRegisterFor(reg, f.ABISelf) v := f.newValueNoBlock(op, t, pos) v.AuxInt = auxInt v.Aux = aux v.Args = nil v.Block = f.Entry newValues = append(newValues, v) addToNV(v, sl)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jun 10 19:44:43 UTC 2024 - 58.4K bytes - Viewed (0) -
src/bytes/bytes_test.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 03 12:58:37 UTC 2024 - 56.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/stablehlo/transforms/compose_uniform_quantized_type_pass.cc
filter_i8_value_attr = mlir::cast<DenseFPElementsAttr>(filter_value) .mapValues(rewriter.getI8Type(), [](const APFloat& val) -> APInt { APSInt convertedInt(/*BitWidth=*/8, /*isUnsigned=*/false); bool ignored; val.convertToInteger(convertedInt, APFloat::rmTowardZero, &ignored);
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 64.6K bytes - Viewed (0) -
docs/en/data/people.yml
avatarUrl: https://avatars.githubusercontent.com/u/52145145?u=f8c9e5c8c259d248e1683fedf5027b4ee08a0967&v=4 url: https://github.com/wu-clan - login: abhint count: 5 avatarUrl: https://avatars.githubusercontent.com/u/25699289?u=b5d219277b4d001ac26fb8be357fddd88c29d51b&v=4 url: https://github.com/abhint - login: anthonycepeda count: 4 avatarUrl: https://avatars.githubusercontent.com/u/72019805?u=60bdf46240cff8fca482ff0fc07d963fd5e1a27c&v=4
Registered: Mon Jun 17 08:32:26 UTC 2024 - Last Modified: Mon Jun 03 01:09:53 UTC 2024 - 55.4K bytes - Viewed (0) -
src/cmd/cgo/gcc.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 20 15:50:06 UTC 2024 - 97K bytes - Viewed (0)