(Sqrt ...) => (FSQRT ...)
(Sqrt32 ...) => (FSQRTS ...)
(Floor ...) => (FFLOOR ...)
(Ceil ...) => (FCEIL ...)
(Trunc ...) => (FTRUNC ...)
(Round ...) => (FROUND ...)
(Copysign x y) => (FCPSGN y x)
(Abs ...) => (FABS ...)
(FMA ...) => (FMADD ...)

// Lowering extension
// Note: we always extend to 64 bits even though some ops don't need that many result bits.
(SignExt8to(16|32|64) ...) => (MOVBreg ...)

	FNMSUBS F1, F2, F3, F4          // ec8110fc
	FNMSUBSCC F1, F2, F3, F4        // ec8110fd
	FSEL F1, F2, F3, F4             // fc8110ee
	FSELCC F1, F2, F3, F4           // fc8110ef
	FABS F1, F2                     // fc400a10
	FNABS F1, F2                    // fc400910
	FABSCC F1, F2                   // fc400a11
	FNABSCC F1, F2                  // fc400911
	FNEG F1, F2                     // fc400850

	case 32: /* fadd fr1,[fr2],fr3 */
		r := p.Reg
		if r == obj.REG_NONE {
			r = p.To.Reg
		}
		o1 = OP_FRRR(c.oprrr(p.As), p.From.Reg, r, p.To.Reg)

	case 33: /* fabs fr1, fr3 */
		o1 = OP_FRRR(c.oprrr(p.As), obj.REG_NONE, p.From.Reg, p.To.Reg)

	case 34: /* mov $con,fr ==> or/add $i,t; mov t,fr */
		a := AADDU
		if o.a1 == C_ANDCON {
			a = AOR
		}

	case 32: // fadd fr1,[fr2],fr3
		r := int(p.Reg)
		if r == 0 {
			r = int(p.To.Reg)
		}
		o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))

	case 33: // fabs fr1, fr3
		o1 = OP_RRR(c.oprrr(p.As), uint32(0), uint32(p.From.Reg), uint32(p.To.Reg))

	case 34: // mov $con,fr
		v := c.regoff(&p.From)
		a := AADDU
		if o.from1 == C_ANDCON {
			a = AOR
		}