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Results 1 - 10 of 15 for ARG1 (0.04 sec)
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src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
{name: "FNMSUBS", argLength: 3, reg: fp31, asm: "FNMSUBS"}, // -arg0 + (arg1 * arg2) {name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD"}, // -arg0 + (arg1 * arg2) {name: "MADD", argLength: 3, reg: gp31, asm: "MADD"}, // +arg0 + (arg1 * arg2) {name: "MADDW", argLength: 3, reg: gp31, asm: "MADDW"}, // +arg0 + (arg1 * arg2), 32-bit {name: "MSUB", argLength: 3, reg: gp31, asm: "MSUB"}, // +arg0 - (arg1 * arg2)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/prepare-quantize.mlir
%0 = "tfl.dequantize"(%arg0) : (tensor<2x3x5x!quant.uniform<u8:f32, 0.1>>) -> tensor<2x3x5xf32> %1 = "tfl.slice"(%0, %arg1, %arg2) : (tensor<2x3x5xf32>, tensor<3xi32>, tensor<3xi32>) -> tensor<?x3x5xf32> func.return %1 : tensor<?x3x5xf32> // CHECK: %0 = "tfl.dequantize"(%arg0) // CHECK: %1 = "tfl.slice"(%0, %arg1, %arg2) // CHECK: %2 = "tfl.quantize"(%1)
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 67.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/prepare-tf.mlir
^bb0(%arg0: tensor<256x32x32x3xf32>, %arg1: tensor<3x3x3x16xf32>, %arg2: tensor<256x3x32x32xf32>) : // OK %0 = "tf.Conv2D"(%arg0, %arg1) {T = "tfdtype$DT_FLOAT", data_format = "NHWC", dilations = [1, 2, 3, 1], padding = "SAME", strides = [1, 4, 5, 1]} : (tensor<256x32x32x3xf32>, tensor<3x3x3x16xf32>) -> tensor<256x8x7x16xf32> // Unsupported data format
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed May 29 07:26:59 UTC 2024 - 59.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/tfrt/tests/mlrt/while_to_map_fn.mlir
func.func private @"map/while_cond"(%arg0: tensor<i32>, %arg1: tensor<i32>, %arg2: tensor<!tf_type.variant<tensor<*xf32>>>, %arg3: tensor<?xf32>) -> tensor<i1> { %cst = "tf.Const"() {device = "/job:localhost/replica:0/task:0/device:CPU:0", value = dense<3> : tensor<i32>} : () -> tensor<i32> %0 = "tf.Less"(%arg0, %cst) {device = "/job:localhost/replica:0/task:0/device:CPU:0"} : (tensor<i32>, tensor<i32>) -> tensor<i1>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Apr 23 06:40:22 UTC 2024 - 68.6K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/decompose_resource_ops.mlir
// CHECK-LABEL: func @reachable_function func.func @reachable_function(%arg0: tensor<*x!tf_type.resource<tensor<2x8xi32>>>, %arg1: tensor<i32>) { // CHECK-NOT: "tf.AssignAddVariableOp" "tf.AssignAddVariableOp"(%arg0, %arg1) {dtype = "tfdtype$DT_INT32"} : (tensor<*x!tf_type.resource<tensor<2x8xi32>>>, tensor<i32>) -> () "tf.OpA"(%arg0, %arg1) {f = @reachable_from_reachable_function} : (tensor<*x!tf_type.resource<tensor<2x8xi32>>>, tensor<i32>) -> () func.return
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed May 22 19:47:48 UTC 2024 - 51.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/stablehlo/tests/passes/lift_quantizable_spots_as_functions.mlir
// CHECK: %[[CONV:.*]] = stablehlo.convolution(%arg0, %arg1) // CHECK: %[[MAX:.*]] = stablehlo.maximum %[[CONV]], %[[CONST]] // CHECK: return %[[MAX]] : tensor<1x3x3x4xf32> // CHECK: } // ----- // CHECK-LABEL: @dot_general_with_relu_fn( // CHECK-SAME: %[[ARG_0:.*]]: tensor<1x1x167xf32>, func.func @dot_general_with_relu_fn(%arg0: tensor<1x1x167xf32>, %arg1: tensor<167x64xf32>) -> tensor<1x1x64xf32> {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri May 10 04:07:09 UTC 2024 - 49.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/experimental/tac/tests/raise-target-subgraphs.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 74.9K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/tpu_cluster_formation.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 22:03:30 UTC 2024 - 53.9K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/stablehlo/tests/passes/quantize_composite_functions.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 09 05:56:10 UTC 2024 - 91.6K bytes - Viewed (0) -
src/cmd/compile/internal/ppc64/ssa.go
// ISEL AuxInt ? arg0 : arg1 // ISELZ is a special case of ISEL where arg1 is implicitly $0. // // AuxInt value indicates conditions 0=LT 1=GT 2=EQ 3=SO 4=GE 5=LE 6=NE 7=NSO. // ISEL accepts a CR bit argument, not a condition as expressed by AuxInt. // Convert the condition to a CR bit argument by the following conversion: // // AuxInt&3 ? arg0 : arg1 for conditions LT, GT, EQ, SO
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 55.4K bytes - Viewed (0)