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Results 1 - 3 of 3 for vsrad (0.05 sec)

  1. src/cmd/asm/internal/asm/testdata/ppc64.s

    	VSRW V1, V2, V3                 // 10611284
    	VSRD V1, V2, V3                 // 106116c4
    	VSR V1, V2, V3                  // 106112c4
    	VSRO V1, V2, V3                 // 1061144c
    	VSLD V1, V2, V3                 // 106115c4
    	VSRAB V1, V2, V3                // 10611304
    	VSRAH V1, V2, V3                // 10611344
    	VSRAW V1, V2, V3                // 10611384
    	VSRAD V1, V2, V3                // 106113c4
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
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  2. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    (Rsh8Ux(64|32|16|8)  x y) && shiftIsBounded(v) => (SRD (MOVBZreg x) y)
    (Rsh64x(64|32|16|8)  x y) && shiftIsBounded(v) => (SRAD x y)
    (Rsh32x(64|32|16|8)  x y) && shiftIsBounded(v) => (SRAW x y)
    (Rsh16x(64|32|16|8)  x y) && shiftIsBounded(v) => (SRAD (MOVHreg x) y)
    (Rsh8x(64|32|16|8)   x y) && shiftIsBounded(v) => (SRAD (MOVBreg x) y)
    
    // Unbounded shifts. Go shifts saturate to 0 or -1 when shifting beyond the number of
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/S390X.rules

    (S(LD|RD|RAD|LW|RW|RAW) x (ANDWconst [c] y)) && c&63 == 63
      => (S(LD|RD|RAD|LW|RW|RAW) x y)
    (SLD  x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SLD  x y)
    (SRD  x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SRD  x y)
    (SRAD x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SRAD x y)
    (SLW  x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SLW  x y)
    (SRW  x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SRW  x y)
    (SRAW x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SRAW x y)
    
    // Match rotate by constant.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 74.3K bytes
    - Viewed (0)
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