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Results 1 - 5 of 5 for bclr (0.05 sec)
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src/cmd/asm/internal/asm/testdata/ppc64.s
BCL $20,CR0LT,$1,LR // 4e800821 BCL $20,CR0LT,$0,LR // 4e800021 BCL $20,CR0LT,LR // 4e800021 BCL $20,CR0GT,LR // 4e810021 BCL 20,CR0LT,LR // BCL $20,CR0LT,LR // 4e800021 BCL 20,undefined_symbol,LR // BCL $20,CR0LT,LR // 4e800021 BCL 20,undefined_symbol+1,LR // BCL $20,CR0GT,LR // 4e810021
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/link/internal/ppc64/asm.go
OP_TOCSAVE = 0xf8410018 // std r2,24(r1) OP_NOP = 0x60000000 // nop OP_BL = 0x48000001 // bl 0 OP_BCTR = 0x4e800420 // bctr OP_BCTRL = 0x4e800421 // bctrl OP_BCL = 0x40000001 // bcl OP_ADDI = 0x38000000 // addi OP_ADDIS = 0x3c000000 // addis OP_LD = 0xe8000000 // ld OP_PLA_PFX = 0x06100000 // pla (prefix instruction word)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 19 20:54:08 UTC 2024 - 63.7K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
AREM, AREMU, AREMW, AREMUW, AADDUW, ASH1ADD, ASH1ADDUW, ASH2ADD, ASH2ADDUW, ASH3ADD, ASH3ADDUW, ASLLIUW, AANDN, AORN, AXNOR, AMAX, AMAXU, AMIN, AMINU, AROL, AROLW, AROR, ARORW, ARORI, ARORIW, ABCLR, ABCLRI, ABEXT, ABEXTI, ABINV, ABINVI, ABSET, ABSETI: p.Reg = p.To.Reg } } // Rewrite instructions with constant operands to refer to the immediate // form of the instruction.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0) -
src/cmd/compile/internal/ppc64/ssa.go
} pp := s.Call(v) // Convert the call into a blrl with hint this is not a subroutine return. // The full bclrl opcode must be specified when passing a hint. pp.As = ppc64.ABCL pp.From.Type = obj.TYPE_CONST pp.From.Offset = ppc64.BO_ALWAYS pp.Reg = ppc64.REG_CR0LT // The preferred value if BI is ignored.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 55.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390X.rules
(RoundToEven x) => (FIDBR [4] x) (Round x) => (FIDBR [1] x) (FMA x y z) => (FMADD z x y) (Sqrt32 ...) => (FSQRTS ...) // Atomic loads and stores. // The SYNC instruction (fast-BCR-serialization) prevents store-load // reordering. Other sequences of memory operations (load-load, // store-store and load-store) are already guaranteed not to be reordered.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0)