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Results 1 - 2 of 2 for REG (0.08 sec)

  1. src/cmd/compile/internal/ssa/debug.go

    	// them.
    	clobbers := uint64(opcodeTable[v.Op].reg.clobbers)
    	for {
    		if clobbers == 0 {
    			break
    		}
    		reg := uint8(bits.TrailingZeros64(clobbers))
    		clobbers &^= 1 << reg
    
    		for _, slot := range locs.registers[reg] {
    			if state.loggingLevel > 1 {
    				state.logf("at %v: %v clobbered out of %v\n", v, state.slots[slot], &state.registers[reg])
    			}
    
    			last := locs.slots[slot]
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jun 10 19:44:43 UTC 2024
    - 58.4K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    (MOVHZreg y:(MOVHBRload _ _)) => y
    
    (MOVHreg y:(MOV(H|B)reg _)) => y // repeat
    
    (MOV(H|HZ)reg y:(MOV(HZ|H)reg x)) => (MOV(H|HZ)reg x)
    
    // W - there are more combinations than these
    
    (MOV(WZ|WZ|WZ|W|W|W)reg y:(MOV(WZ|HZ|BZ|W|H|B)reg _)) => y // repeat
    (MOVWZreg y:(MOV(H|W)BRload _ _)) => y
    
    (MOV(W|WZ)reg y:(MOV(WZ|W)reg x)) => (MOV(W|WZ)reg x)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
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