VGATHERQPD (DX)(Z23*1),K1,Z15 // 6272fd41933c3a
	// EVEX: VCVTPD2DQ with Y suffix (VL=2).
	VCVTPD2DQY (BX), X20  // 62e1ff28e623
	VCVTPD2DQY (R11), X30 // 6241ff28e633
	// XED encoder uses EVEX.X=0 for these; most x86 tools use EVEX.X=1.
	// Either way is OK.
	VMOVQ SP, X20  // 62e1fd086ee4 or 62a1fd086ee4
	VMOVQ BP, X20  // 62e1fd086ee5 or 62a1fd086ee5
	VMOVQ R14, X20 // 62c1fd086ee6 or 6281fd086ee6

	SLL	R5, R6, R7           // 1675a0e1
	SLL.S	R5, R6, R7           // 1675b0e1
	SLL	R5, R7               // 1775a0e1
	SLL.S	R5, R7               // 1775b0e1

// Ops with zero shifts should encode as left shifts
	ADD	R0<<0, R1, R2	     // 002081e0
	ADD	R0>>0, R1, R2	     // 002081e0
	ADD	R0->0, R1, R2	     // 002081e0
	ADD	R0@>0, R1, R2	     // 002081e0
	MOVW	R0<<0(R1), R2        // 002091e7

	VREV32	V5.B16, V5.B16                  // a508206e
	VREV64	V2.S2, V3.S2                    // 4308a00e
	VREV64	V2.S4, V3.S4                    // 4308a04e

// logical ops
//
// make sure constants get encoded into an instruction when it could
	AND	R1@>33, R2
	AND	$(1<<63), R1                        // AND	$-9223372036854775808, R1       // 21004192