(TEQ x (SRL y z)) => (TEQshiftRLreg x y z)
(TEQ x (SRA y z)) => (TEQshiftRAreg x y z)
(CMN x (SLLconst [c] y)) => (CMNshiftLL x y [c])
(CMN x (SRLconst [c] y)) => (CMNshiftRL x y [c])
(CMN x (SRAconst [c] y)) => (CMNshiftRA x y [c])
(CMN x (SLL y z)) => (CMNshiftLLreg x y z)
(CMN x (SRL y z)) => (CMNshiftRLreg x y z)
(CMN x (SRA y z)) => (CMNshiftRAreg x y z)

// prefer *const ops to *shift ops

// CMN
	CMN	$255, R7             // ff0077e3
	CMN	$4278190080, R9      // ff0479e3
	CMN	R9<<30, R7           // 090f77e1
	CMN	R9>>30, R7           // 290f77e1
	CMN	R9->30, R7           // 490f77e1
	CMN	R9@>30, R7           // 690f77e1
	CMN	R9<<R8, R7           // 190877e1
	CMN	R9>>R8, R7           // 390877e1
	CMN	R9->R8, R7           // 590877e1
	CMN	R9@>R8, R7           // 790877e1

		{name: "CMPWconst", argLength: 1, reg: gp1flags, asm: "CMPW", aux: "Int32", typ: "Flags"}, // arg0 compare to auxInt, 32 bit
		{name: "CMN", argLength: 2, reg: gp2flags, asm: "CMN", typ: "Flags", commutative: true},   // arg0 compare to -arg1, provided arg1 is not 1<<63
		{name: "CMNconst", argLength: 1, reg: gp1flags, asm: "CMN", aux: "Int64", typ: "Flags"},   // arg0 compare to -auxInt

	SUBS	R3.UXTX, R8, R9                 // 096123eb
	SUBSW	R17.UXTH, R15, R21              // f521316b
	SUBW	ZR<<14, R19, R13                // 6d3a1f4b
	CMP	R2.SXTH, R13                    // bfa122eb
	CMN	R1.SXTX<<2, R10                 // 5fe921ab
	CMPW	R2.UXTH<<3, R11                 // 7f2d226b
	CMNW	R1.SXTB, R9                     // 3f81212b
	ADD	R1<<1, RSP, R3                  // e367218b