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src/cmd/asm/internal/asm/testdata/arm64.s
FMOVS 0x44332211(R1), F2 // FMOVS 1144201745(R1), F2 FMOVD 0x1000000(R1), F2 // FMOVD 16777216(R1), F2 FMOVD 0x44332211(R1), F2 // FMOVD 1144201745(R1), F2 // shifted or extended register offset. MOVD (R2)(R6.SXTW), R4 // 44c866f8 MOVD (R3)(R6), R5 // 656866f8 MOVD (R3)(R6*1), R5 // 656866f8 MOVD (R2)(R6), R4 // 446866f8
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 08 03:28:17 GMT 2023 - 94.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
// ($1 << 20) | /* MCR/MRC */ // (($2^C_SCOND_XOR) << 28) | /* scond */ // (($3 & 15) << 8) | /* coprocessor number */ // (($5 & 7) << 21) | /* coprocessor operation */ // (($7 & 15) << 12) | /* arm register */ // (($9 & 15) << 16) | /* Crn */ // (($11 & 15) << 0) | /* Crm */ // (($12 & 7) << 5) | /* coprocessor information */ // (1<<4)); /* must be set */ // outcode(AMRC, Always, &nullgen, 0, &g); // }
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 15 20:51:01 GMT 2023 - 69K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
VPGATHERQQ Y0, (R13)(Y1*1), Y2 // c4c2fd91540d00 VPGATHERQQ Y0, 16(R13)(Y1*1), Y2 // c4c2fd91540d10 VPGATHERQQ Y0, 512(R13)(Y1*1), Y2 // c4c2fd91940d00020000 // Test low-8 register for /is4 "hr" operand. VPBLENDVB X0, (BX), X1, X2 // c4e3714c1300 // <XMM0>/Yxr0 tests. SHA256RNDS2 X0, (BX), X2 // 0f38cb13 SHA256RNDS2 X0, (R11), X2 // 410f38cb13
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Apr 11 18:32:50 GMT 2023 - 57.6K bytes - Viewed (0)