VSPLTISH:       "vspltish",
	VSPLTISW:       "vspltisw",
	VSPLTW:         "vspltw",
	VSR:            "vsr",
	VSRAB:          "vsrab",
	VSRAH:          "vsrah",
	VSRAW:          "vsraw",
	VSRB:           "vsrb",
	VSRH:           "vsrh",
	VSRO:           "vsro",
	VSRW:           "vsrw",
	VSUBCUW:        "vsubcuw",
	VSUBFP:         "vsubfp",
	VSUBSBS:        "vsubsbs",
	VSUBSHS:        "vsubshs",

		v.AddArg2(x, y)
		return true
	}
	// match: (SRAW x (MOVWreg y))
	// result: (SRAW x y)
	for {
		x := v_0
		if v_1.Op != OpS390XMOVWreg {
			break
		}
		y := v_1.Args[0]
		v.reset(OpS390XSRAW)
		v.AddArg2(x, y)
		return true
	}
	// match: (SRAW x (MOVHreg y))
	// result: (SRAW x y)
	for {
		x := v_0
		if v_1.Op != OpS390XMOVHreg {

	/*4771*/ uint16(xMatch),
	/*4772*/ uint16(xCondPrefix), 2,
	0x66, 4784,
	0x0, 4778,
	/*4778*/ uint16(xSetOp), uint16(PSRAW),
	/*4780*/ uint16(xReadIb),
	/*4781*/ uint16(xArgMm2),
	/*4782*/ uint16(xArgImm8u),
	/*4783*/ uint16(xMatch),
	/*4784*/ uint16(xSetOp), uint16(PSRAW),
	/*4786*/ uint16(xReadIb),
	/*4787*/ uint16(xArgXmm2),
	/*4788*/ uint16(xArgImm8u),
	/*4789*/ uint16(xMatch),

	// match: (Rsh32x16 x y)
	// cond: shiftIsBounded(v)
	// result: (SRAW x y)
	for {
		x := v_0
		y := v_1
		if !(shiftIsBounded(v)) {
			break
		}
		v.reset(OpPPC64SRAW)
		v.AddArg2(x, y)
		return true
	}
	// match: (Rsh32x16 <t> x y)
	// result: (ISEL [2] (SRAW <t> x y) (SRAWconst <t> x [31]) (CMPconst [0] (ANDconst [0xFFE0] y)))
	for {
		t := v.Type