FNMADDCC:       "fnmadd.",
	FNMSUB:         "fnmsub",
	FNMSUBCC:       "fnmsub.",
	FRSP:           "frsp",
	FRSPCC:         "frsp.",
	FSUB:           "fsub",
	FSUBCC:         "fsub.",
	ISYNC:          "isync",
	LBZ:            "lbz",
	LBZU:           "lbzu",
	LBZUX:          "lbzux",
	LBZX:           "lbzx",
	LFD:            "lfd",
	LFDU:           "lfdu",
	LFDUX:          "lfdux",

				continue
			}
			v.reset(OpS390XFMADD)
			v.AddArg3(x, y, z)
			return true
		}
		break
	}
	// match: (Select0 (FSUB (FMUL y z) x))
	// cond: x.Block.Func.useFMA(v)
	// result: (FMSUB x y z)
	for {
		if v_0.Op != OpS390XFSUB {
			break
		}
		x := v_0.Args[1]
		v_0_0 := v_0.Args[0]
		if v_0_0.Op != OpS390XFMUL {
			break
		}

		return true
	}
	return false
}
func rewriteValuePPC64_OpPPC64FSUB(v *Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (FSUB (FMUL x y) z)
	// cond: x.Block.Func.useFMA(v)
	// result: (FMSUB x y z)
	for {
		if v_0.Op != OpPPC64FMUL {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]