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src/cmd/internal/obj/x86/asm6.go
} } // Mark nonpreemptible instruction sequences. // The 2-instruction TLS access sequence // MOVQ TLS, BX // MOVQ 0(BX)(TLS*1), BX // is not async preemptible, as if it is preempted and resumed on // a different thread, the TLS address may become invalid. if !CanUse1InsnTLS(ctxt) { useTLS := func(p *obj.Prog) bool { // Only need to mark the second instruction, which has
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 146.9K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9.go
size int8 // Text space in bytes to lay operation // A prefixed instruction is generated by this opcode. This cannot be placed // across a 64B PC address. Opcodes should not translate to more than one // prefixed instruction. The prefixed instruction should be written first // (e.g when Optab.size > 8). ispfx bool asmout func(*ctxt9, *obj.Prog, *Optab, *[5]uint32) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 13:55:28 UTC 2024 - 156.1K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/asm7.go
// isRestartable returns whether p is a multi-instruction sequence that, // if preempted, can be restarted. func (c *ctxt7) isRestartable(p *obj.Prog) bool { if c.isUnsafePoint(p) { return false } // If p is a multi-instruction sequence with uses REGTMP inserted by // the assembler in order to materialize a large constant/offset, we // can restart p (at the start of the instruction sequence), recompute
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 201.1K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/asmz.go
{i: 86, as: ALA, a1: C_SAUTO, a6: C_REG}, {i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG}, // undefined (deliberate illegal instruction) {i: 78, as: obj.AUNDEF}, // Break point instruction(0x0001 opcode) {i: 73, as: ABRRK}, // 2 byte no-operation {i: 66, as: ANOPH}, // crypto instructions // KM {i: 124, as: AKM, a1: C_REG, a6: C_REG}, // KDSA {i: 125, as: AKDSA, a1: C_REG, a6: C_REG},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 17:46:09 UTC 2024 - 176.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
// In fact, UMOD will be translated into UREM instruction, and UREM is originally translated into // UDIV and MSUB instructions. But if there is already an identical UDIV instruction just before or // after UREM (case like quo, rem := z/y, z%y), then the second UDIV instruction becomes redundant. // The purpose of this rule is to have this extra UDIV instruction removed in CSE pass.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/debug/elf/elf.go
R_386_TLS_GD_PUSH R_386 = 25 /* pushl instruction for Sun ABI GD sequence */ R_386_TLS_GD_CALL R_386 = 26 /* call instruction for Sun ABI GD sequence */ R_386_TLS_GD_POP R_386 = 27 /* popl instruction for Sun ABI GD sequence */ R_386_TLS_LDM_32 R_386 = 28 /* 32 bit offset to GOT (index,zero) pair */ R_386_TLS_LDM_PUSH R_386 = 29 /* pushl instruction for Sun ABI LD sequence */
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 00:01:16 UTC 2024 - 134.6K bytes - Viewed (0) -
src/cmd/link/internal/ld/data.go
} switch { case ctxt.IsARM(): return n * 20 // Trampolines in ARM range from 3 to 5 instructions. case ctxt.IsARM64(): return n * 12 // Trampolines in ARM64 are 3 instructions. case ctxt.IsPPC64(): return n * 16 // Trampolines in PPC64 are 4 instructions. case ctxt.IsRISCV64(): return n * 8 // Trampolines in RISCV64 are 2 instructions. } panic("unreachable") }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jun 12 15:10:50 UTC 2024 - 100.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/transforms/shape_inference.cc
if (return_ops.size() != 1) return failure(); // Find the return type. auto return_op = return_ops.front(); // Manually fold tf.Cast that precedes the return instruction and only differs // in shape refinement level. bool changed = false; for (OpOperand& arg_op : return_op.getOperation()->getOpOperands()) { Operation* arg_defining_op = arg_op.get().getDefiningOp();
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Sat Jun 08 07:28:49 UTC 2024 - 134.1K bytes - Viewed (0) -
src/cmd/go/alldocs.go
// GOMIPS64 // For GOARCH=mips64{,le}, whether to use floating point instructions. // Valid values are hardfloat (default), softfloat. // GOPPC64 // For GOARCH=ppc64{,le}, the target ISA (Instruction Set Architecture). // Valid values are power8 (default), power9, power10. // GORISCV64 // For GOARCH=riscv64, the RISC-V user-mode application profile for which // to compile. Valid values are rva20u64 (default), rva22u64.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jun 11 16:54:28 UTC 2024 - 142.4K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/translate/import_model.cc
TF_RETURN_IF_ERROR(set_attributes_on_func(ret.node, ret_and_idx.index(), /*is_arg=*/false)); // Lookup the instruction inside the island auto island_op = llvm::cast<mlir::tf_executor::IslandOp>(inst); mlir::Operation* inner_op = &island_op.GetBody().front(); // Remove kRetOp or kDeviceRetOp operation and return its operand.
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed May 01 11:17:36 UTC 2024 - 183.2K bytes - Viewed (0)