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tensorflow/cc/gradients/linalg_grad.cc
return scope.status(); } std::vector<absl::string_view> subs = absl::StrSplit(input_subs, ','); if (subs.size() != 2) { return errors::InvalidArgument("Only 2 inputs are supported"); } std::string x_subs(subs[0]); std::string y_subs(subs[1]); // Add ellipsis for broadcasted dimensions if any operand does not have it.
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Mar 07 23:11:54 UTC 2022 - 20.4K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
case DIVD, DIVDCC, DIVDU, DIVDUCC, DIVDE, DIVDECC, DIVDEU, DIVDEUCC, DIVDO, DIVDOCC, DIVDUO, DIVDUOCC: return true case MODUD, MODSD, MODUW, MODSW: return true case FADD, FADDS, FSUB, FSUBS, FMUL, FMULS, FDIV, FDIVS, FMADD, FMADDS, FMSUB, FMSUBS, FNMADD, FNMADDS, FNMSUB, FNMSUBS, FMULSCC: return true case FADDCC, FADDSCC, FSUBCC, FMULCC, FDIVCC, FDIVSCC: return true
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 10.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 30.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
SUBSW R2.SXTH<<3, R13, R6 // a6ad226b SUBS R21.UXTX<<2, R27, R4 // 646b35eb SUBSW $(44<<12), R6, R9 // SUBSW $180224, R6, R9 // c9b04071 SUBS $(1804<<12), R13, R9 // SUBS $7389184, R13, R9 // a9315cf1 SUBSW R22->28, R6, R7 // c770966b SUBSW R22>>28, R6, R7 // c770566b SUBS R26<<15, R6, R16 // d03c1aeb
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
src/regexp/all_test.go
b.StartTimer() b.ReportAllocs() for i := 0; i < b.N; i++ { subs := re.FindSubmatch(s) if string(subs[0]) != wantSubs { b.Fatalf("FindSubmatch(%q)[0] = %q; want %q", s, subs[0], wantSubs) } if string(subs[1]) != "aab" { b.Fatalf("FindSubmatch(%q)[1] = %q; want %q", s, subs[1], "aab") } } } func BenchmarkFindStringSubmatch(b *testing.B) { b.StopTimer()
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:36:03 UTC 2024 - 25.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/tfr/python/tfr_gen_test.py
Composite = composite.Composite #--- test fn for mlir location --- @Composite('TestInputNOp') def _tfr_loc_test(x): n = 10 x_sum = x[0] for i in range(1, n): x_sum = math_ops.Add(x_sum, x[i]) return x_sum #--- test fn for tfr tensors --- @composite.Composite('TestNoOp') def _tfr_tensor_empty_arg(): pass @composite.Composite('TestIdentityOp')
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Oct 13 16:33:28 UTC 2021 - 28.8K bytes - Viewed (0) -
platforms/documentation/docs/src/docs/userguide/releases/installation.adoc
This is identifiable by the presence of the `gradlew` or `gradlew.bat` files in the root of the project: [listing,subs=+macros] ---- . // <1> ├── gradle │ └── wrapper // <2> ├── gradlew // <3> ├── gradlew.bat // <3> └── ⋮ ---- <1> Project root directory.
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Mon Feb 05 18:33:11 UTC 2024 - 10.6K bytes - Viewed (0) -
platforms/documentation/docs/src/docs/userguide/reference/gradle_wrapper.adoc
[listing,subs=+attributes] ---- $ gradle wrapper --gradle-version {gradleVersion} --distribution-type all include::{snippetsPath}/wrapper/simple/tests/wrapperCommandLine.out[] ---- As a result, you can find the desired information (the generated distribution URL) in the Wrapper properties file: [source,properties,subs=+attributes] ----
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Mon Mar 04 16:15:50 UTC 2024 - 20.7K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/a.out.go
AFRINTIS AFRINTMD AFRINTMS AFRINTND AFRINTNS AFRINTPD AFRINTPS AFRINTXD AFRINTXS AFRINTZD AFRINTZS AFSQRTD AFSQRTS AFSTPD AFSTPQ AFSTPS AFSUBD AFSUBS AHINT AHLT AHVC AIC AISB ALDADDAB ALDADDAD ALDADDAH ALDADDALB ALDADDALD ALDADDALH ALDADDALW ALDADDAW ALDADDB ALDADDD ALDADDH ALDADDLB
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 18 17:56:30 UTC 2023 - 18.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
FSGNJXS F1, F0, F2 // 53211020 FMVXS F0, X5 // d30200e0 FMVSX X5, F0 // 538002f0 FMVXW F0, X5 // d30200e0 FMVWX X5, F0 // 538002f0 FMADDS F1, F2, F3, F4 // 43822018 FMSUBS F1, F2, F3, F4 // 47822018 FNMSUBS F1, F2, F3, F4 // 4b822018 FNMADDS F1, F2, F3, F4 // 4f822018 // 11.8: Single-Precision Floating-Point Compare Instructions FEQS F0, F1, X7 // d3a300a0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 22 04:42:21 UTC 2024 - 16.7K bytes - Viewed (0)