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Results 1 - 10 of 17 for sgdu (1.57 sec)

  1. src/cmd/compile/internal/ssa/_gen/LOONG64.rules

    (Round(32|64)F ...) => (Copy ...)
    
    // comparisons
    (Eq8 x y)  => (SGTU (MOVVconst [1]) (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)))
    (Eq16 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt16to64 x) (ZeroExt16to64 y)))
    (Eq32 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)))
    (Eq64 x y) => (SGTU (MOVVconst [1]) (XOR x y))
    (EqPtr x y) => (SGTU (MOVVconst [1]) (XOR x y))
    (Eq(32|64)F x y) => (FPFlagTrue (CMPEQ(F|D) x y))
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/MIPS64.rules

    (Round(32|64)F ...) => (Copy ...)
    
    // comparisons
    (Eq8 x y)  => (SGTU (MOVVconst [1]) (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)))
    (Eq16 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt16to64 x) (ZeroExt16to64 y)))
    (Eq32 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)))
    (Eq64 x y) => (SGTU (MOVVconst [1]) (XOR x y))
    (EqPtr x y) => (SGTU (MOVVconst [1]) (XOR x y))
    (Eq(32|64)F x y) => (FPFlagTrue (CMPEQ(F|D) x y))
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 41.9K bytes
    - Viewed (0)
  3. test/codegen/mathbits.go

    	// amd64:"NEGL","ADCQ","SBBQ","NEGQ"
    	// loong64: "ADDV", "SGTU"
    	// ppc64x: "ADDC", "ADDE", "ADDZE"
    	// s390x:"ADDE","ADDC\t[$]-1,"
    	// mips64:"ADDV","SGTU"
    	// riscv64: "ADD","SLTU"
    	return bits.Add(x, 7, ci)
    }
    
    func AddZ(x, y uint) (r, co uint) {
    	// arm64:"ADDS","ADC",-"ADCS",-"ADD\t",-"CMP"
    	// amd64:"ADDQ","SBBQ","NEGQ",-"NEGL",-"ADCQ"
    	// loong64: "ADDV", "SGTU"
    	// ppc64x: "ADDC", -"ADDE", "ADDZE"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 18:51:17 UTC 2024
    - 19.6K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/MIPS.rules

    (EqPtr x y) => (SGTUconst [1] (XOR x y))
    (Eq(32|64)F x y) => (FPFlagTrue (CMPEQ(F|D) x y))
    
    (Neq8 x y)  => (SGTU (XOR (ZeroExt8to32 x) (ZeroExt8to32 y)) (MOVWconst [0]))
    (Neq16 x y) => (SGTU (XOR (ZeroExt16to32 x) (ZeroExt16to32 y)) (MOVWconst [0]))
    (Neq32 x y) => (SGTU (XOR x y) (MOVWconst [0]))
    (NeqPtr x y) => (SGTU (XOR x y) (MOVWconst [0]))
    (Neq(32|64)F x y) => (FPFlagFalse (CMPEQ(F|D) x y))
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 35.3K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/MIPSOps.go

    		{name: "SGTU", argLength: 2, reg: gp21, asm: "SGTU", typ: "Bool"},                    // 1 if arg0 > arg1 (unsigned), 0 otherwise
    		{name: "SGTUconst", argLength: 1, reg: gp11, asm: "SGTU", aux: "Int32", typ: "Bool"}, // 1 if auxInt > arg0 (unsigned), 0 otherwise
    		{name: "SGTUzero", argLength: 1, reg: gp11, asm: "SGTU", typ: "Bool"},                // 1 if arg0 > 0 (unsigned), 0 otherwise
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 24K bytes
    - Viewed (0)
  6. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go

    	// store instructions always have the memory operand at the end, no need to reorder
    	// indexed stores handled separately
    	case STB, STBU,
    		STH, STHU,
    		STW, STWU,
    		STD, STDU,
    		STFD, STFDU,
    		STFS, STFSU,
    		STQ, HASHST, HASHSTP:
    		return op + " " + strings.Join(args, ",")
    
    	case FCMPU, FCMPO, CMPD, CMPDI, CMPLD, CMPLDI, CMPW, CMPWI, CMPLW, CMPLWI:
    		crf := int(inst.Args[0].(CondReg) - CR0)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 10.9K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

    		{name: "SGTconst", argLength: 1, reg: gp11, asm: "SGT", aux: "Int64", typ: "Bool"},   // 1 if auxInt > arg0 (signed), 0 otherwise
    		{name: "SGTU", argLength: 2, reg: gp21, asm: "SGTU", typ: "Bool"},                    // 1 if arg0 > arg1 (unsigned), 0 otherwise
    		{name: "SGTUconst", argLength: 1, reg: gp11, asm: "SGTU", aux: "Int64", typ: "Bool"}, // 1 if auxInt > arg0 (unsigned), 0 otherwise
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:19 UTC 2023
    - 25.2K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go

    		{name: "SGTconst", argLength: 1, reg: gp11, asm: "SGT", aux: "Int64", typ: "Bool"},   // 1 if auxInt > arg0 (signed), 0 otherwise
    		{name: "SGTU", argLength: 2, reg: gp21, asm: "SGTU", typ: "Bool"},                    // 1 if arg0 > arg1 (unsigned), 0 otherwise
    		{name: "SGTUconst", argLength: 1, reg: gp11, asm: "SGTU", aux: "Int64", typ: "Bool"}, // 1 if auxInt > arg0 (unsigned), 0 otherwise
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 03:36:31 UTC 2023
    - 25.5K bytes
    - Viewed (0)
  9. src/cmd/vendor/golang.org/x/arch/x86/x86asm/gnu.go

    		if !isMem(inst.Args[1]) {
    			markLastImplicit(&inst, PrefixDataSize)
    		}
    
    	case CVTSD2SI, CVTSS2SI, CVTTSD2SI, CVTTSS2SI,
    		ENTER, FLDENV, FNSAVE, FNSTENV, FRSTOR, LGDT, LIDT, LRET,
    		POP, PUSH, RET, SGDT, SIDT, SYSRET, XBEGIN:
    		markLastImplicit(&inst, PrefixDataSize)
    
    	case LOOP, LOOPE, LOOPNE, MONITOR:
    		markLastImplicit(&inst, PrefixAddrSize)
    
    	case MOV:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:33 UTC 2023
    - 21.4K bytes
    - Viewed (0)
  10. src/cmd/internal/obj/x86/anames.go

    	"SETCS",
    	"SETEQ",
    	"SETGE",
    	"SETGT",
    	"SETHI",
    	"SETLE",
    	"SETLS",
    	"SETLT",
    	"SETMI",
    	"SETNE",
    	"SETOC",
    	"SETOS",
    	"SETPC",
    	"SETPL",
    	"SETPS",
    	"SFENCE",
    	"SGDT",
    	"SHA1MSG1",
    	"SHA1MSG2",
    	"SHA1NEXTE",
    	"SHA1RNDS4",
    	"SHA256MSG1",
    	"SHA256MSG2",
    	"SHA256RNDS2",
    	"SHLB",
    	"SHLL",
    	"SHLQ",
    	"SHLW",
    	"SHLXL",
    	"SHLXQ",
    	"SHRB",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 11 18:32:50 UTC 2023
    - 19.1K bytes
    - Viewed (0)
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