defer func(orig int) { buildcfg.GORISCV64 = orig }(buildcfg.GORISCV64)

	for _, goriscv64 := range []int{20, 22, 23} {
		t.Run(fmt.Sprintf("rva%vu64", goriscv64), func(t *testing.T) {
			buildcfg.GORISCV64 = goriscv64
			testFn(t)
		})
	}
}

func TestRISCV64EndToEnd(t *testing.T) {
	testRISCV64AllProfiles(t, func(t *testing.T) {
		testEndToEnd(t, "riscv64", "riscv64")
	})
}

			// passed RestArgs/AddRestSource
			switch a[1].Type {
			case obj.TYPE_REG:
				prog.Reg = p.getRegister(prog, op, &a[1])
			default:
				prog.AddRestSource(a[1])
			}
		case sys.RISCV64:
			// RISCV64 instructions with one input and two outputs.
			if arch.IsRISCV64AMO(op) {
				prog.From = a[0]
				prog.To = a[1]
				if a[2].Type != obj.TYPE_REG {

<code>softfloat</code>) is made available to assembly code by predefining either
<code>GOMIPS64_hardfloat</code> or <code>GOMIPS64_softfloat</code>.
</p>

<h3 id="riscv64">RISCV64</h3>

<p>
Reference: <a href="/pkg/cmd/internal/obj/riscv">Go RISCV64 Assembly Instructions Reference Manual</a>
</p>

<h3 id="unsupported_opcodes">Unsupported opcodes</h3>

<p>

pkg syscall (freebsd-arm-cgo), type SysProcAttr struct, Jail int #46259
pkg syscall (freebsd-arm), type SysProcAttr struct, Jail int #46259
pkg syscall (freebsd-riscv64-cgo), type SysProcAttr struct, Jail int #46259
pkg syscall (freebsd-riscv64), type SysProcAttr struct, Jail int #46259
pkg testing, func Testing() bool #52600
pkg testing/slogtest, func TestHandler(slog.Handler, func() []map[string]interface{}) error #56345

	{GOOS: "freebsd", GOARCH: "arm"},
	{GOOS: "freebsd", GOARCH: "arm64", CgoEnabled: true},
	{GOOS: "freebsd", GOARCH: "arm64"},
	{GOOS: "freebsd", GOARCH: "riscv64", CgoEnabled: true},
	{GOOS: "freebsd", GOARCH: "riscv64"},
	{GOOS: "netbsd", GOARCH: "386", CgoEnabled: true},
	{GOOS: "netbsd", GOARCH: "386"},
	{GOOS: "netbsd", GOARCH: "amd64", CgoEnabled: true},
	{GOOS: "netbsd", GOARCH: "amd64"},

	register["TP"] = riscv.REG_TP
	register["T0"] = riscv.REG_T0
	register["T1"] = riscv.REG_T1
	register["T2"] = riscv.REG_T2
	register["S0"] = riscv.REG_S0
	register["S1"] = riscv.REG_S1
	register["A0"] = riscv.REG_A0
	register["A1"] = riscv.REG_A1
	register["A2"] = riscv.REG_A2
	register["A3"] = riscv.REG_A3
	register["A4"] = riscv.REG_A4
	register["A5"] = riscv.REG_A5
	register["A6"] = riscv.REG_A6

		}
		for {
			tok = p.nextToken()
			if len(operands) == 0 && len(items) == 0 {
				if p.arch.InFamily(sys.ARM, sys.ARM64, sys.AMD64, sys.I386, sys.Loong64, sys.RISCV64) && tok == '.' {
					// Suffixes: ARM conditionals, Loong64 vector instructions, RISCV rounding mode or x86 modifiers.
					tok = p.nextToken()
					str := p.lex.Text()
					if tok != scanner.Ident {