CJR	X0					// ERROR "cannot use register X0 in rs1"
	CJR	X10, X11				// ERROR "expected no register in rs2"
	CJALR	X0					// ERROR "cannot use register X0 in rs1"
	CJALR	X10, X11				// ERROR "expected no register in rd"
	CBEQZ	X5, 1(PC)				// ERROR "expected integer prime register in rs1"
	CBNEZ	X5, 1(PC)				// ERROR "expected integer prime register in rs1"
	CLI	$3, X0					// ERROR "cannot use register X0 in rd"

			p.errorf("register list: bad low register in `[%s`", loName)
		}
		return
	}
	if tok := p.next().ScanToken; tok != '-' {
		p.errorf("register list: expected '-' after `[%s`, found %s", loName, tok)
		return
	}
	hiName := p.next().String()
	hi, ok := p.arch.Register[hiName]
	if !ok {
		p.errorf("register list: bad high register in `[%s-%s`", loName, hiName)
		return
	}

	VADDVX		X10, V2, V1, V3			// ERROR "invalid vector mask register"
	VADDVI		$15, V4, V1, V2			// ERROR "invalid vector mask register"
	VSUBVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
	VSUBVX		X10, V2, V1, V3			// ERROR "invalid vector mask register"
	VRSUBVX		X10, V2, V1, V3			// ERROR "invalid vector mask register"
	VRSUBVI		$15, V4, V1, V2			// ERROR "invalid vector mask register"

	register["A0"] = riscv.REG_A0
	register["A1"] = riscv.REG_A1
	register["A2"] = riscv.REG_A2
	register["A3"] = riscv.REG_A3
	register["A4"] = riscv.REG_A4
	register["A5"] = riscv.REG_A5
	register["A6"] = riscv.REG_A6
	register["A7"] = riscv.REG_A7
	register["S2"] = riscv.REG_S2
	register["S3"] = riscv.REG_S3
	register["S4"] = riscv.REG_S4
	register["S5"] = riscv.REG_S5
	register["S6"] = riscv.REG_S6

        kryo.register(double[].class);
        kryo.register(Float.class);
        kryo.register(float[].class);
        kryo.register(Boolean.class);
        kryo.register(boolean[].class);
        kryo.register(Byte.class);
        kryo.register(byte[].class);
        kryo.register(Short.class);
        kryo.register(short[].class);
        kryo.register(Character.class);
        kryo.register(char[].class);

	CASPD	(R2, R3), (R2), (R9, R10)                        // ERROR "destination register pair must start from even register"
	CASPD	(R2, R4), (R2), (R8, R9)                         // ERROR "source register pair must be contiguous"
	CASPD	(R2, R3), (R2), (R8, R10)                        // ERROR "destination register pair must be contiguous"

        // Get the queryProcessor that was registered in parent class
        queryProcessor = ComponentUtil.getComponent("queryProcessor");

        // Register all query commands needed for testing
        new TermQueryCommand().register();
        new MatchAllQueryCommand().register();
        new PhraseQueryCommand().register();
        new BooleanQueryCommand().register();
        new PrefixQueryCommand().register();

        lifecyleTasks.put(DOCKER, project.getTasks().register(taskPrefix + ".docker"));
        lifecyleTasks.put(DOCKER_UBI, project.getTasks().register(taskPrefix + ".docker-ubi"));
        lifecyleTasks.put(DOCKER_IRONBANK, project.getTasks().register(taskPrefix + ".docker-ironbank"));
        lifecyleTasks.put(DOCKER_CLOUD, project.getTasks().register(taskPrefix + ".docker-cloud"));

	MOVM.IB	[R0-R4], (F1)      // ERROR "illegal base register"
	MOVM.DB	[R0-R4], (F1)      // ERROR "illegal base register"
	MOVW	R0<<0(F1), R1      // ERROR "illegal base register"
	MOVB	R0<<0(F1), R1      // ERROR "illegal base register"
	MOVW	R1, R0<<0(F1)      // ERROR "illegal base register"
	MOVB	R2, R0<<0(F1)      // ERROR "illegal base register"
	MOVF	0x00ffffff(F2), F1 // ERROR "illegal base register"

	handler2 := func(req *testRequest) (resp *testResponse, err *RemoteErr) {
		r := RemoteErr(req.String)
		return nil, &r
	}
	errFatal(h1.Register(local, handler1))
	errFatal(h2.Register(local, handler2))

	errFatal(h1.Register(remote, handler1))
	errFatal(h2.Register(remote, handler2))

	// local to remote connection
	remoteConn := local.Connection(remoteHost)
	const testPayload = "Hello Grid World!"