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Results 1 - 6 of 6 for q1 (0.07 sec)
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src/cmd/asm/internal/asm/testdata/arm64error.s
VPMULL V1.D1, V2.H4, V3.Q1 // ERROR "invalid arrangement" VPMULL V1.H4, V2.H4, V3.Q1 // ERROR "operand mismatch" VPMULL V1.D2, V2.D2, V3.Q1 // ERROR "operand mismatch" VPMULL V1.B16, V2.B16, V3.H8 // ERROR "operand mismatch" VPMULL2 V1.D2, V2.H4, V3.Q1 // ERROR "invalid arrangement"
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Fri Dec 08 03:28:17 UTC 2023 - 37.8K bytes - Viewed (0) -
android/guava/src/com/google/common/cache/Striped64.java
* provided. */ static final class Cell { volatile long p0, p1, p2, p3, p4, p5, p6; volatile long value; volatile long q0, q1, q2, q3, q4, q5, q6; Cell(long x) { value = x; } final boolean cas(long cmp, long val) { return UNSAFE.compareAndSwapLong(this, valueOffset, cmp, val); }
Registered: Fri Nov 01 12:43:10 UTC 2024 - Last Modified: Fri Jun 14 17:55:55 UTC 2024 - 11.5K bytes - Viewed (0) -
cmd/metacache-entries_test.go
wantOk: true, }, { name: "one-q1", m: metaCacheEntries{inputSerialized[0], inputSerialized[4], inputSerialized[4], inputSerialized[4]}, r: metadataResolutionParams{dirQuorum: 1, objQuorum: 1, strict: false}, wantSelected: &inputSerialized[0], wantOk: true, }, { name: "one-q1-strict",
Registered: Sun Nov 03 19:28:11 UTC 2024 - Last Modified: Sun Jan 02 17:15:06 UTC 2022 - 31.6K bytes - Viewed (0) -
guava/src/com/google/common/hash/Striped64.java
* provided. */ static final class Cell { volatile long p0, p1, p2, p3, p4, p5, p6; volatile long value; volatile long q0, q1, q2, q3, q4, q5, q6; Cell(long x) { value = x; } final boolean cas(long cmp, long val) { return UNSAFE.compareAndSwapLong(this, valueOffset, cmp, val); }
Registered: Fri Nov 01 12:43:10 UTC 2024 - Last Modified: Fri Jun 14 17:55:55 UTC 2024 - 11.5K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm64.go
case "D2": if isIndex { return errors.New("invalid register extension") } a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2D & 15) << 5) case "Q1": if isIndex { return errors.New("invalid register extension") } a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1Q & 15) << 5) case "B": if !isIndex { return nil }
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Thu Sep 29 09:04:58 UTC 2022 - 10.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
VMOVI $146, V22.B16 // 56e6044f VORR V25.B16, V22.B16, V15.B16 // cf1eb94e VPMULL V2.D1, V1.D1, V3.Q1 // 23e0e20e VPMULL2 V2.D2, V1.D2, V4.Q1 // 24e0e24e VPMULL V2.B8, V1.B8, V3.H8 // 23e0220e VPMULL2 V2.B16, V1.B16, V4.H8 // 24e0224e
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0)