r1 = val64 >> shift
	}
	if shift >= 0 && shift < 32 {
		// arm64:"LSR",-"CSEL"
		r2 = val32 >> shift
	}
	if shift >= 0 && shift < 16 {
		// arm64:"LSR",-"CSEL"
		r3 = val16 >> shift
	}
	if shift >= 0 && shift < 8 {
		// arm64:"LSR",-"CSEL"
		r4 = val8 >> shift
	}
	return r1, r2, r3, r4
}

		return op + " " + args[0] + "," + args[1] + "," + args[2]
	case SYNC:
		if args[0] == "$1" {
			return "LWSYNC"
		}
		return "HWSYNC"

	case ISEL:
		return "ISEL " + args[3] + "," + args[1] + "," + args[2] + "," + args[0]

	// store instructions always have the memory operand at the end, no need to reorder
	// indexed stores handled separately
	case STB, STBU,
		STH, STHU,

	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ISEL [a] x (MOVDconst [0]) z)
	// result: (ISELZ [a] x z)
	for {
		a := auxIntToInt32(v.AuxInt)
		x := v_0
		if v_1.Op != OpPPC64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 {
			break
		}
		z := v_2
		v.reset(OpPPC64ISELZ)
		v.AuxInt = int32ToAuxInt(a)
		v.AddArg2(x, z)
		return true
	}
	// match: (ISEL [a] (MOVDconst [0]) y z)
	// result: (ISELZ [a^0x4] y z)

		// ISEL  arg2 ? arg0 : arg1
		// ISELZ arg1 ? arg0 : $0
		// auxInt values 0=LT 1=GT 2=EQ 3=SO (summary overflow/unordered) 4=GE 5=LE 6=NE 7=NSO (not summary overflow/not unordered)
		// Note, auxInt^4 inverts the comparison condition. For example, LT^4 becomes GE, and "ISEL [a] x y z" is equivalent to ISEL [a^4] y x z".
		{name: "ISEL", argLength: 3, reg: crgp21, asm: "ISEL", aux: "Int32", typ: "Int32"},

identifies a CR then the resulting condition is set in that field
to be read by a later branch or isel instruction. Within these fields,
bits are set to indicate less than, greater than, or equal conditions.

Once an instruction sets a condition, then a subsequent branch, isel or
other instruction can read the condition field and operate based on the
bit settings.

Examples:

			return "0"
		}
		return arg.String()
	case CondReg:
		// The CondReg can either be found in a CMP, where the
		// condition register field is being set, or in an instruction
		// like a branch or isel that is testing a bit in a condition
		// register field.
		if arg == CR0 && strings.HasPrefix(inst.Op.String(), "cmp") {
			return "" // don't show cr0 for cmp instructions
		} else if arg >= CR0 {

	RET

zeroshift:
	CMP     R6, $0          // x is null, nothing to copy
	BEQ     done
	CMP     R6, R3          // if x is same as z, nothing to copy
	BEQ     done
	CMP     R7, R4
	ISEL    $0, R7, R4, R7  // Take the lower bound of lengths of x,z
	SLD     $3, R7, R7
	SUB     R6, R3, R11     // dest - src
	CMPU    R11, R7, CR2    // < len?
	BLT     CR2, backward   // there is overlap, copy backwards

		LDP.P	16(b_ptr), (acc0, acc1)
		CSEL	EQ, acc0, x0, x0
		CSEL	EQ, acc1, x1, x1
		LDP.P	16(b_ptr), (acc2, acc3)
		CSEL	EQ, acc2, x2, x2
		CSEL	EQ, acc3, x3, x3
		LDP.P	16(b_ptr), (acc4, acc5)
		CSEL	EQ, acc4, y0, y0
		CSEL	EQ, acc5, y1, y1
		LDP.P	16(b_ptr), (acc6, acc7)
		CSEL	EQ, acc6, y2, y2
		CSEL	EQ, acc7, y3, y3
		LDP.P	16(b_ptr), (acc0, acc1)
		CSEL	EQ, acc0, t0, t0
		CSEL	EQ, acc1, t1, t1

			isEq := WorkloadInstancesEqual(testCase.comparer, testCase.comparee)
			isEqReverse := WorkloadInstancesEqual(testCase.comparee, testCase.comparer)

			if isEq != isEqReverse {
				t.Errorf(
					"returned different for reversing arguments for structs: %v , and %v",
					testCase.comparer,
					testCase.comparee,
				)
			}
			if isEq != testCase.shouldEq {
				t.Errorf(

	_COMMENT

	// newlines and punctuation tokens are allowed as ASCII codes.
)

func (k tokenKind) isComment() bool {
	return k == _COMMENT || k == _EOLCOMMENT
}

// isEOL returns whether a token terminates a line.
func (k tokenKind) isEOL() bool {
	return k == _EOF || k == _EOLCOMMENT || k == '\n'
}

// startToken marks the beginning of the next input token.