if reg1 && reg2 && (inst.Opcode>>24 == 0xDC || inst.Opcode>>24 == 0xDE) {
			switch inst.Op {
			case FDIV:
				inst.Op = FDIVR
			case FDIVR:
				inst.Op = FDIV
			case FSUB:
				inst.Op = FSUBR
			case FSUBR:
				inst.Op = FSUB
			case FDIVP:
				inst.Op = FDIVRP
			case FDIVRP:
				inst.Op = FDIVP
			case FSUBP:
				inst.Op = FSUBRP
			case FSUBRP:
				inst.Op = FSUBP
			}
		}

		{above1e23, 'g', -1, "1.0000000000000001e+23"},

		{5e-304 / 1e20, 'g', -1, "5e-324"},
		{-5e-304 / 1e20, 'g', -1, "-5e-324"},
		{fdiv(5e-304, 1e20), 'g', -1, "5e-324"},   // avoid constant arithmetic
		{fdiv(-5e-304, 1e20), 'g', -1, "-5e-324"}, // avoid constant arithmetic

		{32, 'g', -1, "32"},
		{32, 'g', 0, "3e+01"},

		{100, 'x', -1, "0x1.9p+06"},

	MOVW	R1, R6
	MOVW	R3, R7
	CMPBLE	R6, R7, L4
	WORD	$0xED109050	//cdb	%f1,.L128-.L38(%r9)
	BYTE	$0x00
	BYTE	$0x19
	BGE	L37
	BVS	L37
	FMOVD	72(R9), F6
	FSUB	F1, F6
	MOVH	$0x1000, R3
	FDIV	F1, F6
	MOVH	$0x1000, R1
L17:
	WFMDB	V6, V6, V1
	FMOVD	64(R9), F2
	FMOVD	56(R9), F4
	FMOVD	48(R9), F3
	WFMADB	V1, V3, V2, V3
	FMOVD	40(R9), F2
	WFMADB	V1, V2, V4, V2
	FMOVD	32(R9), F4

	case DIVD, DIVDCC, DIVDU, DIVDUCC, DIVDE, DIVDECC, DIVDEU, DIVDEUCC, DIVDO, DIVDOCC, DIVDUO, DIVDUOCC:
		return true
	case MODUD, MODSD, MODUW, MODSW:
		return true
	case FADD, FADDS, FSUB, FSUBS, FMUL, FMULS, FDIV, FDIVS, FMADD, FMADDS, FMSUB, FMSUBS, FNMADD, FNMADDS, FNMSUB, FNMSUBS, FMULSCC:
		return true
	case FADDCC, FADDSCC, FSUBCC, FMULCC, FDIVCC, FDIVSCC:
		return true

		}

	case FST, FSTP, FISTTP, FIST, FISTP, FBSTP:
		if len(args) == 1 {
			args = append(args, "st0")
		}

	case FLD, FXCH, FCOM, FCOMP, FIADD, FIMUL, FICOM, FICOMP, FISUBR, FIDIV, FUCOM, FUCOMP, FILD, FBLD, FADD, FMUL, FSUB, FSUBR, FISUB, FDIV, FDIVR, FIDIVR:
		if len(args) == 1 {
			args = []string{"st0", args[0]}
		}

	case MASKMOVDQU, MASKMOVQ, XLATB, OUTSB, OUTSW, OUTSD:
	FixSegment:

	// special case Pow(-0, y) = +Inf for finite y < 0 and not an odd integer
	FIDBR	$5, F2, F4		//F2 translate to integer F4
	FCMPU	F2, F4
	BNE	zeroNotOdd			// y is not an (odd) integer and y < 0
	FMOVD	$(2.0), F4
	FDIV	F4, F2			// F2 = F2 / 2.0
	FIDBR	$5, F2, F4		//F2 translate to integer F4
	FCMPU	F2, F4
	BNE	negZeroOddInt		// y is an odd integer and y < 0
	BR	zeroNotOdd			// y is not an (odd) integer and y < 0

negZeroGtZero:

	FSUBS	F2, F13                // b30b00d2
	FSUB	F3, F12                // b31b00c3
	FMULS	F4, F11                // b31700b4
	FMUL	F5, F10                // b31c00a5
	FDIVS	F6, F9                 // b30d0096
	FDIV	F7, F8                 // b31d0087
	FABS	F1, F2                 // b3100021
	FSQRTS	F3, F4                 // b3140043
	FSQRT	F5, F15                // b31500f5
	FIEBR	$0, F0, F1             // b3570010

		args[0], args[1] = args[1], args[0]
		fallthrough

	case FCMP, FCMPE:
		if _, ok := inst.Args[1].(Imm); ok {
			args[1] = "$(0.0)"
		}
		fallthrough

	case FADD, FSUB, FMUL, FNMUL, FDIV, FMAX, FMIN, FMAXNM, FMINNM, FCSEL, FMADD, FMSUB, FNMADD, FNMSUB:
		if strings.HasSuffix(op, "MADD") || strings.HasSuffix(op, "MSUB") {
			args[2], args[3] = args[3], args[2]
		}
		if r, ok := inst.Args[0].(Reg); ok {

		{name: "POPCNTB", argLength: 1, reg: gp11, asm: "POPCNTB"}, // number of set bits in each byte of arg0 placed in corresponding byte

		{name: "FDIV", argLength: 2, reg: fp21, asm: "FDIV"},   // arg0/arg1
		{name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS"}, // arg0/arg1

		{name: "DIVD", argLength: 2, reg: gp21, asm: "DIVD", typ: "Int64"},   // arg0/arg1 (signed 64-bit)

(Mul32 ...) => (MULW ...)
(Mul16 x y) => (MULW (SignExt16to32 x) (SignExt16to32 y))
(Mul8 x y)  => (MULW (SignExt8to32 x)  (SignExt8to32 y))
(Mul(64|32)F ...) => (FMUL(D|S) ...)

(Div(64|32)F ...) => (FDIV(D|S) ...)

(Div64 x y [false])  => (DIV x y)
(Div64u ...) => (DIVU ...)
(Div32 x y [false])  => (DIVW x y)
(Div32u ...) => (DIVUW ...)
(Div16 x y [false])  => (DIVW  (SignExt16to32 x) (SignExt16to32 y))