Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 10 of 17 for cmovnz (0.22 sec)

  1. src/cmd/vendor/golang.org/x/arch/x86/x86asm/intel.go

    	SETAE:     "setnb",
    	SETA:      "setnbe",
    	SETGE:     "setnl",
    	SETNE:     "setnz",
    	SETG:      "setnle",
    	SETE:      "setz",
    	CMOVAE:    "cmovnb",
    	CMOVA:     "cmovnbe",
    	CMOVGE:    "cmovnl",
    	CMOVNE:    "cmovnz",
    	CMOVG:     "cmovnle",
    	CMOVE:     "cmovz",
    	LCALL:     "call far",
    	LJMP:      "jmp far",
    	LRET:      "ret far",
    	ICEBP:     "int1",
    	MOVSD_XMM: "movsd",
    	XLATB:     "xlat",
    }
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Nov 29 22:23:32 UTC 2017
    - 11.7K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/x86/anames.go

    	"FADDW",
    	"FBLD",
    	"FBSTP",
    	"FCHS",
    	"FCLEX",
    	"FCMOVB",
    	"FCMOVBE",
    	"FCMOVCC",
    	"FCMOVCS",
    	"FCMOVE",
    	"FCMOVEQ",
    	"FCMOVHI",
    	"FCMOVLS",
    	"FCMOVNB",
    	"FCMOVNBE",
    	"FCMOVNE",
    	"FCMOVNU",
    	"FCMOVU",
    	"FCMOVUN",
    	"FCOMD",
    	"FCOMDP",
    	"FCOMDPP",
    	"FCOMF",
    	"FCOMFP",
    	"FCOMI",
    	"FCOMIP",
    	"FCOML",
    	"FCOMLP",
    	"FCOMW",
    	"FCOMWP",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 11 18:32:50 UTC 2023
    - 19.1K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/MIPS.rules

    (Rsh32Ux32 <t> x y) => (CMOVZ (SRL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
    (Rsh32Ux16 <t> x y) => (CMOVZ (SRL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
    (Rsh32Ux8 <t> x y)  => (CMOVZ (SRL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
    
    (Rsh16Ux32 <t> x y) => (CMOVZ (SRL <t> (ZeroExt16to32 x) y) (MOVWconst [0]) (SGTUconst [32] y))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 35.3K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/s390x/a.out.go

    	AMULLW
    	AMULLD
    	AMULHD
    	AMULHDU
    	AMLGR
    	ASUB
    	ASUBC
    	ASUBV
    	ASUBE
    	ASUBW
    	ANEG
    	ANEGW
    
    	// integer moves
    	AMOVWBR
    	AMOVB
    	AMOVBZ
    	AMOVH
    	AMOVHBR
    	AMOVHZ
    	AMOVW
    	AMOVWZ
    	AMOVD
    	AMOVDBR
    
    	// conditional moves
    	AMOVDEQ
    	AMOVDGE
    	AMOVDGT
    	AMOVDLE
    	AMOVDLT
    	AMOVDNE
    	ALOCR
    	ALOCGR
    
    	// find leftmost one
    	AFLOGR
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Sep 05 16:41:03 UTC 2023
    - 12.4K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/s390x/ssa.go

    		switch t.Size() {
    		case 1:
    			if t.IsSigned() {
    				return s390x.AMOVB
    			} else {
    				return s390x.AMOVBZ
    			}
    		case 2:
    			if t.IsSigned() {
    				return s390x.AMOVH
    			} else {
    				return s390x.AMOVHZ
    			}
    		case 4:
    			if t.IsSigned() {
    				return s390x.AMOVW
    			} else {
    				return s390x.AMOVWZ
    			}
    		case 8:
    			return s390x.AMOVD
    		}
    	}
    	panic("bad load type")
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 01:26:58 UTC 2023
    - 27.1K bytes
    - Viewed (0)
  6. src/cmd/internal/obj/ppc64/a.out.go

    	AFRSPCC
    	AFSUB
    	AFSUBCC
    	AFSUBS
    	AFSUBSCC
    	AISEL
    	AMOVMW
    	ALBAR
    	ALHAR
    	ALSW
    	ALWAR
    	ALWSYNC
    	AMOVDBR
    	AMOVWBR
    	AMOVB
    	AMOVBU
    	AMOVBZ
    	AMOVBZU
    	AMOVH
    	AMOVHBR
    	AMOVHU
    	AMOVHZ
    	AMOVHZU
    	AMOVW
    	AMOVWU
    	AMOVFL
    	AMOVCRFS
    	AMTFSB0
    	AMTFSB0CC
    	AMTFSB1
    	AMTFSB1CC
    	AMULHW
    	AMULHWCC
    	AMULHWU
    	AMULHWUCC
    	AMULLW
    	AMULLWCC
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 16K bytes
    - Viewed (0)
  7. test/codegen/memcombine.go

    	// amd64:`MOVWLZX\s\(.*\),`,-`MOVB`,-`OR`
    	// ppc64le:`MOVHZ\s`,-`MOVBZ`
    	// arm64:`MOVHU\s\(R[0-9]+\),`,-`MOVB`
    	// s390x:`MOVHBR\s\(.*\),`
    	// ppc64:`MOVHBR\s`,-`MOVBZ`
    	return binary.LittleEndian.Uint16(b)
    }
    
    func load_le16_idx(b []byte, idx int) uint16 {
    	// amd64:`MOVWLZX\s\(.*\),`,-`MOVB`,-`OR`
    	// ppc64le:`MOVHZ\s`,-`MOVBZ`
    	// ppc64:`MOVHBR\s`,-`MOVBZ`
    	// arm64:`MOVHU\s\(R[0-9]+\)\(R[0-9]+\),`,-`MOVB`
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 21 19:45:41 UTC 2024
    - 29.7K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/MIPSOps.go

    		// order of parameters is reversed so we can use resultInArg0 (OpCMOVZ result arg1 arg2-> CMOVZ arg2reg, arg1reg, resultReg)
    		{name: "CMOVZ", argLength: 3, reg: gp31, asm: "CMOVZ", resultInArg0: true},
    		{name: "CMOVZzero", argLength: 2, reg: regInfo{inputs: []regMask{gp, gpg}, outputs: []regMask{gp}}, asm: "CMOVZ", resultInArg0: true},
    
    		{name: "MOVWF", argLength: 1, reg: fp11, asm: "MOVWF"},     // int32 -> float32
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 24K bytes
    - Viewed (0)
  9. test/codegen/mathbits.go

    func IterateBits(n uint) int {
    	i := 0
    	for n != 0 {
    		// amd64/v1,amd64/v2:"BSFQ",-"CMOVEQ"
    		// amd64/v3:"TZCNTQ"
    		i += bits.TrailingZeros(n)
    		n &= n - 1
    	}
    	return i
    }
    
    func IterateBits64(n uint64) int {
    	i := 0
    	for n != 0 {
    		// amd64/v1,amd64/v2:"BSFQ",-"CMOVEQ"
    		// amd64/v3:"TZCNTQ"
    		i += bits.TrailingZeros64(n)
    		n &= n - 1
    	}
    	return i
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 18:51:17 UTC 2024
    - 19.6K bytes
    - Viewed (0)
  10. src/crypto/internal/nistec/p256_asm_amd64.s

    	MOVQ acc3, t3
    	// Add in case the operand was > p256
    	ADDQ $-1, acc0
    	ADCQ p256const0<>(SB), acc1
    	ADCQ $0, acc2
    	ADCQ p256const1<>(SB), acc3
    	ADCQ $0, mul0
    	CMOVQNE t0, acc0
    	CMOVQNE t1, acc1
    	CMOVQNE t2, acc2
    	CMOVQNE t3, acc3
    	// If condition is 0, keep original value
    	TESTQ DX, DX
    	CMOVQEQ acc4, acc0
    	CMOVQEQ acc5, acc1
    	CMOVQEQ acc6, acc2
    	CMOVQEQ acc7, acc3
    	// Store result
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 39.8K bytes
    - Viewed (0)
Back to top