VSETVLI		$-1, E32, M2, TA, MA, X12	// ERROR "must be in range [0, 31] (5 bits)"
	VSETVL		X10, X11			// ERROR "expected integer register in rs1 position"
	VLE8V		(X10), X10			// ERROR "expected vector register in vd position"
	VLE8V		(V1), V3			// ERROR "expected integer register in rs1 position"
	VSE8V		X10, (X10)			// ERROR "expected vector register in vs1 position"

	FNES	F1, (X5)			// ERROR "needs an integer register output"

	//
	// "V" Standard Extension for Vector Operations, Version 1.0
	//
	VSETIVLI	X10, E32, M2, TA, MA, X12	// ERROR "expected immediate value"
	VLE8V		(X10), V1, V3			// ERROR "invalid vector mask register"
	VSE8V		V3, V1, (X10)			// ERROR "invalid vector mask register"
	VLSE8V		(X10), X10, V1, V3		// ERROR "invalid vector mask register"